3D advanced integration technology for heterogeneous systems

Vivet, Pascal; Bernard, Christian; Clermidy, Fabien; Dutoit, Denis; Guthmuller, Èric; Panades, Ivan-Miro; Pillonnet, Gaël; Thonnart, Yvain; Garnier, A.; Lattard, Didier; Jouve, A.; Bana, F.; Mourier, Thierry; Chéramy, S.

doi:10.1109/3dic.2015.7334468

Cited by 11 publications

(4 citation statements)

References 10 publications

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“…In addition, the channels in the passive interposer should be standardized to make modular SoC design. Hence, there is increase in research of active interposer [16,4,2,17,18,19,20,21] both in industry and academia. We also consider an active interposer substrate for designing the interposer network.…”

Section: Modular 25d Soc Integrationmentioning

confidence: 99%

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Majumder,

Kim,

Huang

et al. 2019

Preprint

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The increase in design cost and complexity have motivated designers to adopt modular design of System on Chip (SoC) by integrating independently designed small chiplets. However, it introduces new challenges for correctness validation, increasing chances of forming deadlock in the system involving multiple chiplets. Although there have been many solutions available for deadlock freedom in flat networks, the study on deadlock issue in chiplet-based systems is still in its infancy.A recent study suggests adding extra turn restrictions as a viable solution for this problem. However, imposing extra turn restrictions reduces chiplet design flexibility and interposer design complexity. In addition, it may lead to non-minimal route and traffic imbalance forming hotspots, resulting in high latency and low throughput.We propose Remote Control (RC), a simple routing oblivious deadlock avoidance scheme. Our proposal is based on two key observations. First, packets with destinations in the current chiplet are blocked by packets with destinations outside the chiplet. Second, deadlock always involves multiple boundary routers 1 . Hence, we segregate different traffics to alleviate mutual blocking at the chiplet's boundary routers. Along with guarantee of deadlock freedom and performance enhancements, our simple RC scheme also provides more routing flexibility to both chiplet and SoC designers, as compared to the state-of-the-art.

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Section: Modular 25d Soc Integrationmentioning

confidence: 99%

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Majumder,

Kim,

Huang

et al. 2019

Preprint

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“…The surface-mounted package used in the traditional space-borne microwave system is planar integration; the pin frequency is limited, the square shell shape is not conducive to cavity separation, and the matching restriction of thermal expansion coefficient limits the system integration of a large number of microwave dies [1][2][3][4]. With the development of special substrate materials such as silicon-based and laminated fabrication technology, system-level encapsulated microwave components based on wafers, substrates with three-dimensional (3D) heterogeneous integration, have been developed [5][6][7][8]. However, they are usually limited by their internal microwave interconnection structures, and their application frequencies cannot be further expanded.…”

Section: Introductionmentioning

confidence: 99%

Space-Borne System-in-Package Based on High Reliability Microwave Interconnections

Wan

et al. 2023

Electronics

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With the increasing demand for multi-function and highly integrated space-borne microwave products, a three-dimensional heterogeneous integration based on special substrates and other systems-in-package has difficulty with meeting the requirements of high reliability in space. Through simulation, the thermal-deformation resistance of traditional interconnections meets the requirements of high reliability, but its transmission performance at high frequency is poor. Based on the above, a novel microwave horizontal coaxial transition structure with good thermal-deformation resistance and excellent microwave characteristics is proposed. The design formula of the structure is derived, and the basic size of the structure can be quickly calculated. The transition structure and a vertical matching structure can realize microwave interconnection by combining microstrip impedance transformation and gold-ribbon interconnection. The complex microwave circuit is laid out and partitioned in a three-dimensional way, and thus a space-borne microwave metallic system-in-package method based on high reliability microwave interconnections is implemented. A Ka-band receiving system-in-package is used as an example to carry out the actual test and validation. The better characteristics of the Ka-band receiving channel on the satellite are obtained, and its excellent reliability is verified by the temperature cycle and mechanical vibration test.

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“…There are two types of stacking technologies to integrate multiple silicon chips . Three‐dimensional (3D) stacking technology makes it possible to stack various dies together . It takes multiple silicon chips and places one on top of the other .…”

Section: Introductionmentioning

confidence: 99%

An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems

Dadashi

Reshadi

Reza

et al. 2019

Trans Emerging Tel Tech

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In 2.5D stacking technology, multiple chips have stacked side-by-side on a silicon interposer layer. The network-on-chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked vertically. The network-on-chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock-free routing algorithm on the CPU layer and interposer layer is essential. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform interconnection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub-networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner.Trans Emerging Tel Tech. 2019;30:e3747.wileyonlinelibrary.com/journal/ett

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3D advanced integration technology for heterogeneous systems

Cited by 11 publications

References 10 publications

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Space-Borne System-in-Package Based on High Reliability Microwave Interconnections

An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems

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