An expandable topology with low wiring congestion for silicon interposer‐based network‐on‐chip systems

Abstract

In 2.5D stacking technology, multiple chips have stacked side-by-side on a silicon interposer layer. The network-on-chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked vertically. The network-on-chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock-free routing algorithm on the CPU layer and interposer layer is essential. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform interconnection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub-networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner.Trans Emerging Tel Tech. 2019;30:e3747.wileyonlinelibrary.com/journal/ett

Management of Load-Balancing Data Stream in Interposer-Based Network-on-Chip Using Specific Virtual Channels

“…Placing on the two horizontal sides, more memory stacks are integrated through the silicon interposer area. For this reason, higher capacities and higher bandwidth are achievable compared to 3D technology [5][6][7]. In this figure, the differences between 2.5D and 3D technologies have been shown.…”

“…In Figure 1(a), it may be seen that memory blocks are located on the silicon interposer and connected with the interposer layer through interface nodes. There are also two disparate types of traffic: the first one is the core-to-core traffic associated with the interaction between cores and the second is the core-to-memory traffic, which is responsible for transferring packets between memory blocks and cores [1,6]. Core-to-core traffic, which is known for coherence traffic, should be distributed across all the networks in order to avoid protocol-level deadlock [1].…”

“…Furthermore, 3D NoC architecture faces some issues, namely, thermal and cooling troubles, the lack of EDA tools, and many problems related to the test [19]; for this reason, 2.5D NoC, which is based on silicon stacking, has recently been popular [5,20]. That is, many design tools [1,6,7,21] support 2.5D stacking architecture and likewise, many use it for further GPU designs [1,22]. It is worth mentioning that this newly emerged technology is already seen in many commercial products [1,23,24].…”