3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities

Fazzi,; Canegallo,; Ciccarelli,; Magagni,; Natali,; Jung, E.; Rolandi,; Guerrieri,

doi:10.1109/isscc.2007.373441

Cited by 24 publications

(8 citation statements)

References 9 publications

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“…22 compares this proposed design with leading published research. Works [32] and [33] implement near-field capacitive communication, and [11], [13], [34], [35] use inductive communication (as adopted in this paper). Fig.…”

Section: Energy-per-bit Evaluationmentioning

confidence: 99%

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

Fletcher

Das

Mak

2020

IEEE J. Solid-State Circuits

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Wireless 3D integration using Inductive Coupling Links (ICLs) has recently gained attention as a low-cost alternative to through silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3D integration using ICLs is often criticised for its inferior energy efficiency compared to conventional approaches. To address this challenge, in this paper, we present a low-energy ICL transceiver that combines: (1) a spike-latency encoding scheme (to reduce the number of energyexpensive analogue transmit pulses by encoding data in the timedomain), and (2) a tuneable current driver (to minimise the transmit energy depending on the given integration scenario). The proposed transceiver is modelled mathematically, simulated in 0.35um, 65nm and 28nm CMOS technologies, and experimentally validated in a 2-tier 3D stacked silicon test-chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4pJ/bit, representing a reduction >13% when compared to previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). Simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7× improvement in energy-per-bit compared to state-of-theart implementations across the same communication distance, marking an important progression towards cost and energy efficient 3D integration.

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Section: Energy-per-bit Evaluationmentioning

confidence: 99%

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

Fletcher

Das

Mak

2020

IEEE J. Solid-State Circuits

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“…11 compares this proposed design with leading published research. Works [7] and [8] implement near-field capacitive communication, and [1], [3]- [5] use inductive communication (as adopted in this paper). Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration

Fletcher

Mak

Das

2019

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35um CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110um, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3× improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulsecode mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.

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“…As shown in Fig. 1, the chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits communicate through capacitive coupling between top-layer metal pads [6][7][8][9][10][11][12][13][14]. The high-bandwidth inter-chip I/O design for high-speed 3D-packaing has become more challenging to be implemented in nanoscale CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications

Hsiao

Chen

Lin

et al. 2011

2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the cosimulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.

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3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities

Cited by 24 publications

References 9 publications

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration

Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications

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