3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices

Marconi, Thomas; Lu, Yi; Bertels, Koen; Gaydadjiev, Georgi

doi:10.1007/978-3-642-12133-3_19

Cited by 16 publications

(20 citation statements)

References 10 publications

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“…The only algorithm we are aware of targeting 3D FPGAs is presented in [4]; whereas other existing work only target 2D FPGAs (e.g. [5], [6], [7]). …”

Section: Introduction and Related Workmentioning

confidence: 99%

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Marconi

Mitra

2011

2011 International Conference on Field-Programmable Technology

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Abstract-The recent emergence of 3D partially reconfigurable FPGAs implies that we need efficient online hardware task scheduling and placement algorithms for such architectures. However, the algorithms available in the literature for 3D FPGAs create a "blocking-effect". That is, these algorithms tend to make a wrong decision in finding a location of each arriving hardware task during runtime scheduling and placement on 3D partially reconfigurable FPGAs. This leads to currently scheduled tasks blocking future hardware tasks from being scheduled and satisfying their deadlines. We need to solve this problem to maximize the performance of partially reconfigurable runtime systems implemented using 3D chip technology. We propose a novel placement and scheduling algorithm with a blocking-aware heuristic to make better decisions at runtime. Based on evaluation using both synthetic and real workloads, our algorithm reduces deadline miss rate by 61% with 15% longer runtime overhead compared to state-of-the-art algorithms.

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“…The only algorithm we are aware of targeting 3D FPGAs is presented in [4]; whereas other existing work only target 2D FPGAs (e.g. [5], [6], [7]). …”

Section: Introduction and Related Workmentioning

confidence: 99%

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Marconi

Mitra

2011

2011 International Conference on Field-Programmable Technology

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“…Marconi et al were inspired by [1] and presented a novel 3D total contiguous surface heuristic in order to equip the scheduler with "blockingawareness" capability [2]. Subsequently, Lu et al created the first scheduling algorithm that considers the data dependencies and communication amongst hardware tasks, and between tasks and external devices [3].…”

Section: Related Workmentioning

confidence: 99%

Hardware Task Scheduling for Partially Reconfigurable FPGAs

Charitopoulos

Koidis

Papadimitriou

et al. 2015

Lecture Notes in Computer Science

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Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a run time system manager for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM considers the runtime status of each task and region, e.g. busy, idle, scheduled for reconfiguration/execution etc., to execute tasks. Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and RR reservation for future reconfiguration and execution. We validate its correctness using our RTSM to execute an image processing application on a ZedBoard platform. We also evaluate its features within a simulation framework, and find that despite the technology limitations, our approach can give promising results in terms of quality of scheduling. IntroductionReconfiguration can dynamically adapt the functionality of hardware systems by swapping in and out HW tasks. To select the proper resource for loading and triggering HW task reconfiguration and execution in partially reconfigurable systems with FPGAs, efficient and flexible runtime system support is needed [6]. In this paper we propose and implement a Run-Time System Manager (RTSM) incorporating efficient scheduling mechanisms that balance effectively the execution of HW and SW tasks and the use of physical resources. We aim to execute as fast as possible a given application, without exhausting the physical resources. Our motivation during the development of RTSM was to find ways to overcome the strict technology restrictions imposed by the Xilinx PR flow [8]:  Static partitioning of the reconfigurable surface in reconfigurable regions (RR).

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“…An interesting idea proposed in this work is the possibility of reusing the already configured tasks on the device, even when they implement only a part of the total functionality required: computation can start in these tasks, while the task that implements the complete functionality is being configured, and once the latter is ready, the partially processed data can be transferred to it. In [17], the same authors propose the so-called 3D Total Contiguous Surface (3DTCS) heuristic that is intended to avoid task placements that will be an obstacle for other incoming tasks in the future. 3DCTS computes the total contiguous surface of the computation volume defined by a given task, that is, the occupied area in time, with the computation volumes of other executing tasks and with the device's boundaries.…”

Section: Related Workmentioning

confidence: 99%

“…As a result of including the time domain in the analysis, 3DA outperformed 2DA. In fact, 3DA is currently one of the most effective heuristics for efficiently allocating hardware tasks onto reconfigurable devices, being used or serving as inspiration for other approaches in the field (e.g., 3DCTS [17]).…”

Section: Related Workmentioning

confidence: 99%

“…As presented in Section 3, several research efforts can be found in the technical literature to improve the computation density when allocating hardware tasks onto an FPGA device. These approaches mainly include bin packing-based algorithms (e.g., [21,22]) and adjacency-based heuristics (e.g., [17,28,29]). However, bin-packing algorithms do not consider the effect that placing a task into the "bin box" involves in allocating future tasks, and adjacency-based heuristics have a vision of only one resource row/column beyond the boundaries of already placed tasks.…”

Section: Allocation Algorithmsmentioning

confidence: 99%

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Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

Iturbe

Benkrid

Hong

et al. 2013

International Journal of Reconfigurable Computing

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This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.

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3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices

Cited by 16 publications

References 10 publications

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Hardware Task Scheduling for Partially Reconfigurable FPGAs

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

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