3D direct vertical interconnect microprocessors test vehicle

Mayega, John; Erdogan, Okan; Belemjian, Paul M.; Zhou, Kun; McDonald, J. F.; Kraft, R.P.

doi:10.1145/764808.764846

Cited by 22 publications

(4 citation statements)

References 2 publications

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“…Examples includes caches, TLBs, branch predictors, reorder buffers, register files and others. Many previous 3D SRAM designs have proposed organizations that split the bit-arrays across two or more layers [25,32,38,53]. As discussed earlier in this paper, such an approach can provide significant performance and power benefits, but it is unfortunately incompatible with our stated goal of making 3D completely optional.…”

Section: Extensible Sram Structuresmentioning

confidence: 99%

A modular 3d processor for flexible product design and technology migration

Loh

2008

Proceedings of the 5th Conference on Computing Frontiers

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The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core" or AMD's "K8") that is used throughout all of the PC market segments from laptops to servers. To differentiate the products, manufacturers rely on speed binning, different cache sizes, and varying the number of cores. In this paper, we propose using 3D integration to provide a new, but complementary, approach to providing product differentiation. Past research on using 3D to improve performance has focused on the construction of "fully 3D" circuits where functional blocks are partitioned across two or more layers. This approach forces one of two undesirable situations: (1) all products must be implemented in, and therefore pay the cost of, 3D or (2) a 3D-implemented processor is designed for the high-end/high-performance markets and a separate 2D microarchitecture must be designed for the lower-cost markets thereby incurring significant additional design effort and engineering cost. We present a modular processor architecture where 3D can be used to enhance performance within a single unified design and also provides for a more gradual migration path toward fully 3D-integrated designs. To make this work, we describe a generic technique of using "phantom" components where the baseline processor may believe that 3D-stacked resources exist, but are currently unavailable. Simply using 3D to stack more L2 cache provides a 15.1% average performance benefit, but our proposal increases performance by 25.4%.

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Section: Extensible Sram Structuresmentioning

confidence: 99%

A modular 3d processor for flexible product design and technology migration

Loh

2008

Proceedings of the 5th Conference on Computing Frontiers

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“…Rahman and Reif [8] evaluate system-level performance metrics in 3D integrated circuits. Other works explore cache implementations: [9,10] (where the authors present a delay and energy model, 3DCacti, to explore different 3D design options of partitioning a cache) and [11]; design of 3D arithmetic circuits: [12] (it is focused on a 3D microprocessor test vehicle and demonstrates the speed advantages derived from the 3D integration) and [13] (they show how a barrel shifter implemented in 3D exhibits a 9% reduction in latency with a simultaneous 8% reduction in energy). Finally, other works evaluate wire benefits in full microprocessors: [14] (where a 3D structure of is examined and applied to a real x86 deeply pipelined high performance microprocessor.…”

Section: Related Workmentioning

confidence: 99%

Thermal modeling and analysis of 3D multi-processor chips

2010

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“…Third, recently, there has been a great deal of interest in the 3D ICs, such as 3D-integrated caches [5-7, 26, 27], 3D-integrated register files [28], 3D-integrated arithmetic units [12,[24][25][26], 3D-integrated content addressable memories (CAMs) circuits [10,11], clocking schemes for 3D-integrated circuits [29], 3D-integrated processors [11,21,22,[30][31][32][33], 3D-integrated systems-on-a-chip [34,35], 3D-integrated FPGA [36][37][38] and design automation tools for 3D-integrated designs [11,35,[39][40][41][42]. However, little mixed-signal 3D-integrated system which includes analog, digital and radio frequency circuits is reported.…”

Section: Icmentioning

confidence: 99%

“…26. The BGA balls are directly attached on the back side of the bottom die of 3D chip through TSV and RDL routing.…”

mentioning

confidence: 99%

Design methodologies and digital circuit implementation for 3DIC wireless sensor node (WSN) system

Lan¹

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In recent years, there is a great deal of interest in the three-dimensional integrated circuit (3D IC). By stacking multiple active device layers with vertical interconnect, 3D IC technology provides great opportunities for designers to meet power and performance requirements. In this research, the innovative 3D IC technology is employed as a basic tool. In addition to the conventional horizontal dimension, active devices are stacked in the vertical dimension in 3D IC technology. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, so that delay, power consumption, and area can be reduced. The design problem of miniaturized wireless sensor node has been explored and a digital core design in wireless sensor node is proposed in this work. The design aims to provide an efficient solution for recording users' bio-vital data, as well as to transmit, extract and deposit the information on the platform. This capability serves to

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3D direct vertical interconnect microprocessors test vehicle

Cited by 22 publications

References 2 publications

A modular 3d processor for flexible product design and technology migration

A modular 3d processor for flexible product design and technology migration

Thermal modeling and analysis of 3D multi-processor chips

Design methodologies and digital circuit implementation for 3DIC wireless sensor node (WSN) system

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