Thermal modeling and analysis of 3D multi-processor chips

Ayala, José L.; Sridhar, Arvind; Cuesta, David

doi:10.1016/j.vlsi.2010.06.002

Cited by 34 publications

(13 citation statements)

References 29 publications

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“…where k ef f is the effective thermal conductivity, which depends on the ratio of the TSV areas versus the total areas considered [10]. The top view of a TSV cell is shown in Fig.…”

Section: Problem Formulationmentioning

confidence: 99%

“…Traditional approaches treat TSVs as a vertical lumped thermal resistor in each physical plane and its resistance value is proportional to the length and inversely proportional to the diameter of the TTSV [9], [10]. The TSV as a one dimensional (1D) network implies heat flows only in the vertical direction towards the heat sink of the system.…”

Section: Introductionmentioning

confidence: 99%

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Compact lateral thermal resistance modeling and characterization for TSV and TSV array

Liu

Swarup

Tan

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Thermal issues are among the major concerns for 3D stacked ICs, and Through silicon vias (TSVs) are used to effectively reduce the temperature of 3D ICs. Normally, TSV is considered as a good thermal conductor in its vertical direction, and its vertical thermal resistance has been studied extensively. However, lateral heat transfer of TSVs, which is also important, was largely ignored in the past. In this paper, we propose an accurate physics-based model for lateral resistance of TSVs in terms of physical and material parameters, and discuss the conditions valid for model accuracy. In addition to modeling the lateral thermal resistance of a single TSV, the proposed thermal model is also applicable to TSV arrays or TSV farms. We show that the TSV insulation linear and space between TSVs could impose a significant impact on TSV thermal behavior. The new TSV thermal model can be easily integrated into a finite difference based thermal analysis framework to improve analysis efficiency. The accuracy of the model is validated against a commercial finite element tool -COMSOL. Experimental results show that the proposed TSV lateral thermal resistance model is very accurate for both a single TSV and TSV arrays.

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“…where k ef f is the effective thermal conductivity, which depends on the ratio of the TSV areas versus the total areas considered [10]. The top view of a TSV cell is shown in Fig.…”

Section: Problem Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compact lateral thermal resistance modeling and characterization for TSV and TSV array

Liu

Swarup

Tan

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…The time to failure of integrated circuits can be predicted as e Ea=kT , where T is the absolute temperature, k is the Boltzmann's constant, and Ea is the activation energy of the failure mechanism being accelerated by the increased temperature [5]. Furthermore, the electromigration of metal wires is influenced by the temperature gradient, can also reduce the reliability of integrated circuits.…”

Section: Introductionmentioning

confidence: 99%

Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system

Guo

Zhang

Yao

et al. 2016

IEICE Electron. Express

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Multi-core 3D IC is a new solution for greater quantity of cores, but with critical challenge of internal thermal. The interlayer cooling system is introduced for this problem, and expends the design space of task allocation. This work proposes a thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system, integrated with simulated annealing method. The results show that the maximal temperature and temperature gradient reduced by 19.4°C and 5.1°C respectively, compared to the randomized policy, and obtain better balance between normal and extreme cases than traditional ranking policy, in a design of 3 active device layers.

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“…The time to failure of integrated circuits can be predicted as e Ea=kT , where T is the absolute temperature, k is the Boltzmann's constant, and Ea is the activation energy of the failure mechanism being accelerated by the increased temperature [4]. Furthermore, the electromigration of metal wires is influenced by the temperature gradient, can also reduce the reliability of integrated circuits [5].…”

Section: Introductionmentioning

confidence: 99%

“…Floorplaning algorithms are for minimizing chip area in original, but the thermal-aware floorplanning algorithms decide the placement of units according to their thermal characters, to reduce and even out the internal temperature of processor through thermal diffusion effect [10]. The units are classified as hot and cool ones, are considered as thermal sources and sinks separately, and arranged by the multi-objective algorithm, liner programming or simulated annealing methods [4]. In the interlayer cooling system, the distribution of heat removal coefficient is also influenced by the relative location of units and fluid cavities.…”

Section: Introductionmentioning

confidence: 99%

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system

Guo

Zhang

Yao

2015

IEICE Electron. Express

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3D ICs is a solution for multi-core processors, with critical challenge of internal thermal problem. A new solution for this problem is interlayer cooling system, which expands the floorplan design space of micro-processors in 3D ICs. This work proposes a floorplanner for multicore processor in 3D ICs with interlayer cooling system, integrated with greedy and particle swarm optimization method. The results show that the maximal temperature and temperature gradient reduced by 10.3°C and 9.2°C respectively, compared with the baseline design in 3 active device layers.

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Thermal modeling and analysis of 3D multi-processor chips

Cited by 34 publications

References 29 publications

Compact lateral thermal resistance modeling and characterization for TSV and TSV array

Compact lateral thermal resistance modeling and characterization for TSV and TSV array

Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system

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