3D DRAM Design and Application to 3D Multicore Systems

Sun, Hongbin; Liu, Jibang; Anigundi, Rakesh; Zheng, Nanning; Lü, Jian–Qiang; Rose, K.; Zhang, Tong

doi:10.1109/mdt.2009.105

Cited by 48 publications

(25 citation statements)

References 10 publications

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“…In this section we outline the performance advantages of a 3-D crypto co-processor and quantify several relevant metrics including latency and clock speed of current competing co-processor approaches. [26,41].…”

Section: Thermal Analysismentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community. Traditionally, crypto coprocessors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor. These methods have their drawbacks and limitations in terms of tamper-resistance, side-channel immunity and performance. In this work we propose a new class of co-processors that are "snapped-on" to the main processor using 3-D integration, and we investigate their security ramifications. These 3-D co-processors hold many advantages over previous implementations. This paper begins with an overview of 3-D integration and its prior applications. We then outline security threat models relevant to crypto co-processors and discuss the advantages and disadvantages of using a dedicated 3-D crypto co-processor compared to traditional, commodity, off-chip crypto co-processors. We also discuss the performance improvements that can be gained from using a 3-D approach.

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Section: Thermal Analysismentioning

confidence: 99%

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

Valamehr

Huffmire

Irvine

et al. 2012

Cryptography and Security: From Theory to Applications

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“…Others have investigated system architectures using 3D-integrated on-chip DRAM [17], [18], [19], [20]. In [3], Weis et al present a design space exploration of SoCs with 3D-stacked DRAM and in [21] the authors show an overview of 3D-integrated DRAMs and the challenges associated with it.…”

Section: Related Workmentioning

confidence: 99%

A distributed interleaving scheme for efficient access to WideIO DRAM memory

Seiculescu

Benini

Micheli

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's WIDE-IO) 3D-stacked memories, to extract maximal effective bandwidth and minimize latency for main memory access. We propose a new distributed interleaved access method that leverages the on-chip interconnect to simplify the design and implementation of the DRAM controller, without impacting performance compared to traditional centralized implementations. We perform experiments on realistic workload for a mobile communication and multimedia platform and show that our proposed distributed interleaving memory access method improves the overall throughput while minimally impacting the performance of latency sensitive communication flows.

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“…Several researchers have proposed leveraging alternative technologies such as 3D stacking [11,15,20] and proximity communication [4] to address the manycore memory bandwidth challenge. Both technologies would offer either local DRAM physically packaged with the processor chip, or a tightly integrated multichip memory module connected to the processors via standard electrical interconnect.…”

Section: Related Workmentioning

confidence: 99%

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Beamer

Sun

Kwon

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by processor and DRAM pin-bandwidth density and by total DRAM chip power, including off-chip signaling, cross-chip interconnect, and bank access energy. In this work, we redesign the DRAM mainmemory system using a proposed monolithically integrated siliconphotonic technology and show that our photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues. Photonics can provide high aggregate pin-bandwidth density through dense wavelength-division multiplexing. Photonic signaling provides energy-efficient communication, which we exploit to not only reduce chip-to-chip interconnect power but to also reduce cross-chip interconnect power by extending the photonic links deep into the actual PIDRAM chips. To complement these large improvements in interconnect bandwidth and power, we decrease the number of bits activated per bank to improve the energy efficiency of the PIDRAM banks themselves. Our most promising design point yields approximately a 10× power reduction for a single-chip PIDRAM channel with similar throughput and area as a projected future electrical-only DRAM. Finally, we propose optical power guiding as a new technique that allows a single PIDRAM chip design to be used efficiently in several multi-chip configurations that provide either increased aggregate capacity or bandwidth.

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3D DRAM Design and Application to 3D Multicore Systems

Cited by 48 publications

References 10 publications

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

A distributed interleaving scheme for efficient access to WideIO DRAM memory

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

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