3D Embedding and Interconnection of Ultra Thin (&amp;#x226A; 20 &amp;#x003BC;m) Silicon Dies

Iker, F.; Tezcan, Deniz Sabuncuoglu; Teixeira, Ricardo Cotrin; Soussan, Philippe; Moor, Piet De; Beyne, Eric; Baert, Kris

doi:10.1109/eptc.2007.4469735

Cited by 19 publications

(11 citation statements)

References 6 publications

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“…In the previous studies at imec, via opening onto embedded dies was performed using the polymer's photosensitivity (minimum via pitch was 40 µm) [1][2][3]. In the actual process, many dimensions exhibit important variability (e.g.…”

Section: µM Pad Pitch Via Opening Resultsmentioning

confidence: 99%

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Ultra thin die embedding technology with 20μm-pitch interconnection

Funaya

Buisson

Preter

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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A novel approach is presented for polymer die embedding and 3D stacking technology, applicable to 3D LSI packaging with consideration to future die specifications. Two main parts are described here; a newly developed die thinning process and an integration process employing via opening by deep reactive ion etching (DRIE). The target minimum pad pitch on embedded dies was 20 µm, considering the finest pad pitch in the next 5 to 10 years. Thin dies embedded in polymer allow for the use of narrow-pitch copper pillars beside the dies for vertical conductive connections. 20 µm-pitch pads on approximately 15 µm-thick die were successfully connected using such 3D interconnections to a base wafer, and confirmed by electrical measurements. IntroductionDie embedding in polymer is a key technology for fabricating system-in-packages (SIP). This technology allows for the interconnection of different devices in a single package, thus allowing heterogeneous integration. Such technology can be applied to 3D die stacking without the need for through Si vias (TSVs), using multiple dies with different sizes and pad-layout. The recent demands for packaging die with a large number of fine pitch connections and in thinner packages require new fabrication techniques. In this paper, we report on a wafer-level die embedding technology, employing ultra thin die and fine interconnection pitch, using our so-called ultra thin chip stacking (UTCS) approach developed at imec [1,3]. Compared to die embedding fabricated in printed wire board (PWB) lines [4,5], typical benefits in a wafer-level fabrication approach are accurate photo-lithography patterning and possible use of dry process steps.Fine pitch interconnection in this die embedding process is strongly influenced by the die thickness variation, generated impurities, and remaining glue material of the die thinning process. Therefore, we first developed a novel die thinning process. Next the fine pitch embedding process was developed. Dies used in our fabrication process have a thickness ranging from 14 to 20 µm, and this thickness range is defined by process. Employing thin die allows us a large selection range of spin-on dielectric materials while maintaining a low wafer warpage, thanks to the limited polymer thickness. Minimum pad pitch designed for our embedded die is 20 µm, corresponding to the pitch assumed to be used in LSI products in the five years based on ITRS roadmap [6]. We propose a novel die thinning process to fabricate 15 µm-thick die with less than 10 µm-size edge chipping, using wafer bonding to a glass carrier using a high-heat-resistance (>200 o C) temporary bonding material. A polymer dry etching approach to achieve 20 µm-pitch via interconnections is developed. Finally, 20 µm-pitch

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Section: µM Pad Pitch Via Opening Resultsmentioning

confidence: 99%

“…This glass carrier allows handling of fragile thin silicon wafer. Previously, imec reported on thin die singulation based on DRIE as grooving technique [2]. This method had the advantage of avoiding chipping at the die edge.…”

Section: Processmentioning

confidence: 99%

Ultra thin die embedding technology with 20μm-pitch interconnection

Funaya

Buisson

Preter

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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“…Currently, the industry relies on prototype equipment optimized to handle thin silicon, e.g., flip chip die bonders with adapted tooling and special release tapes [6,[20][21][22]. Temporary carriers may be used to support the thinned dice during assembly [23]. In some instances, the ultrathin chips were assembled using a mask aligner [24].…”

Section: Contact Methods For Ultrathin Die Packagingmentioning

confidence: 99%

Laser-assisted ultrathin die packaging: Insights from a process study

Marinov

Swenson

Atanasov

et al. 2013

Microelectronic Engineering

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“…Embedded interconnections are another enabler for 3-D integration where the thin dies are embedded on top of each other in a polymer and connection between them is achieved by Cu pillars [4] and electroplating. Standard fabrication of these interconnects requires patterning of the embedding polymer which can be performed using different techniques such as lithography, dry etch or laser micromachining.…”

Section: (C) Flycutting On High Topography Polymermentioning

confidence: 99%

Diamond bit cutting for processing high topography wafers

Agarwal

Pham

Cotrin

et al. 2009

2009 11th Electronics Packaging Technology Conference

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In this paper we report the results of diamond bit cutting on metals, such as Cu and Sn, polymers, temporary glue and polyimide. Diamond bit cutting is an attractive, fast and economically viable option when processing on high topography wafers is required, or when smooth surface finish is required. Diamond bit cutting can planarize the surface of the high topography features on which conventional IC processing steps can be performed with ease. IntroductionWith the new developments in 3D integration there is a high demand for processing wafers with high topography. Conventional IC processing steps like lithography, wafer bonding, deposition steps etc. show limited success on high topography samples. Chemical-mechanical polishing (CMP) is a method to planarize the surface of metal (damascene process); however CMP is not available as a technique to use in post-passivation processing in a packaging environment due to high cost.Diamond bit cutting, also referred as flycutting, is a very attractive option when processing on high topography wafers is required as it can planarize the surface of such high topography wafers, on which conventional IC processing steps can be performed with ease. It can also be used to planarize the surface of electroplated metal/solder bumps or bonding rings, which in turn will result in high yielding bonds.Flycutting is a rather new technique. It is used to planarize metal bumps [1], [2], [3], polymers or polyimide. In the flycutting process, a diamond cutting bit moves over the wafer performing a milling type operation, removing all material it comes into contact with (Fig. 1). The cutting bit is kept at a fixed distance from the chuck table, so, if the substrate is properly attached to the tool table (using vacuum in this case) and has itself only minimal thickness variations (~1 μm for silicon wafer, typically), the distance of the bit to the wafer surface is properly controlled. Fig. 1 shows the schematic of how flycutting planarizes the surface of a wafer with high topography. Usually metals like Cu, Sn and Au embedded in polymer are cut using this technique. The polymer can be easily removed after flycutting, if required.In this paper we present the results of flycutting on metals like Cu and Sn. We also present the flycutting results on high topography surfaces in the presence of polymers, temporary glue and polyimide.

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3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Cited by 19 publications

References 6 publications

Ultra thin die embedding technology with 20μm-pitch interconnection

Ultra thin die embedding technology with 20μm-pitch interconnection

Laser-assisted ultrathin die packaging: Insights from a process study

Diamond bit cutting for processing high topography wafers

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3D Embedding and Interconnection of Ultra Thin (&#x226A; 20 &#x003BC;m) Silicon Dies

Cited by 19 publications

References 6 publications

Ultra thin die embedding technology with 20&#x03BC;m-pitch interconnection

Ultra thin die embedding technology with 20&#x03BC;m-pitch interconnection

Laser-assisted ultrathin die packaging: Insights from a process study

Diamond bit cutting for processing high topography wafers

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Product

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3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Ultra thin die embedding technology with 20μm-pitch interconnection

Ultra thin die embedding technology with 20μm-pitch interconnection