Ultra thin die embedding technology with 20μm-pitch interconnection

Abstract

A novel approach is presented for polymer die embedding and 3D stacking technology, applicable to 3D LSI packaging with consideration to future die specifications. Two main parts are described here; a newly developed die thinning process and an integration process employing via opening by deep reactive ion etching (DRIE). The target minimum pad pitch on embedded dies was 20 µm, considering the finest pad pitch in the next 5 to 10 years. Thin dies embedded in polymer allow for the use of narrow-pitch copper pillars beside the dies for vertical conductive connections. 20 µm-pitch pads on approximately 15 µm-thick die were successfully connected using such 3D interconnections to a base wafer, and confirmed by electrical measurements. IntroductionDie embedding in polymer is a key technology for fabricating system-in-packages (SIP). This technology allows for the interconnection of different devices in a single package, thus allowing heterogeneous integration. Such technology can be applied to 3D die stacking without the need for through Si vias (TSVs), using multiple dies with different sizes and pad-layout. The recent demands for packaging die with a large number of fine pitch connections and in thinner packages require new fabrication techniques. In this paper, we report on a wafer-level die embedding technology, employing ultra thin die and fine interconnection pitch, using our so-called ultra thin chip stacking (UTCS) approach developed at imec [1,3]. Compared to die embedding fabricated in printed wire board (PWB) lines [4,5], typical benefits in a wafer-level fabrication approach are accurate photo-lithography patterning and possible use of dry process steps.Fine pitch interconnection in this die embedding process is strongly influenced by the die thickness variation, generated impurities, and remaining glue material of the die thinning process. Therefore, we first developed a novel die thinning process. Next the fine pitch embedding process was developed. Dies used in our fabrication process have a thickness ranging from 14 to 20 µm, and this thickness range is defined by process. Employing thin die allows us a large selection range of spin-on dielectric materials while maintaining a low wafer warpage, thanks to the limited polymer thickness. Minimum pad pitch designed for our embedded die is 20 µm, corresponding to the pitch assumed to be used in LSI products in the five years based on ITRS roadmap [6]. We propose a novel die thinning process to fabricate 15 µm-thick die with less than 10 µm-size edge chipping, using wafer bonding to a glass carrier using a high-heat-resistance (>200 o C) temporary bonding material. A polymer dry etching approach to achieve 20 µm-pitch via interconnections is developed. Finally, 20 µm-pitch

A study on the effect of wire bonding interconnects of BCB capped CPW to CPW on LTCC substrate

“…Also, die embedding is a key technology for fabricating of system‐in‐packages (SiP). Embedding of semiconductor chips into substrates has several advantages; high degree of miniaturization, short electrical interconnect, geometrical well controlled interconnect, and a homogeneous mechanical environment of a chip resulting in good reliability . Different embedding technologies have been reported.…”

A Descum Review for Cleaning Surfaces in Polymer Embedded Process Flows

“…The descum step plays a particularly important role in integrated passives and die embedding processing. Embedded interconnections are typically used in integrated passives processes or in die embedding processes, eg: The UTCS (or Ultra Thin Chip Stacking) chip embedding technology under development at IMEC [1][2][3][4][5]. Cross section examples of part of such processing are illustrated in Fig.…”