3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory

Wang, Hong; Bathen,; Shao, Yikai; Dutt, Nikil

doi:10.1109/date.2012.6176694

Cited by 22 publications

(10 citation statements)

References 8 publications

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“…However, although 3D flash memories present a good opportunity to further increase the capacity as well as reduce the bit cost, some research reports from the industries and the academics have pointed out that multiple potential problems impose huge challenges on adopting 3D flash memories in a typical storage system [22], [81], [76]. In particular, big block [76], [22] and program disturbance [22], [81] are two critical issues that should be considered for garbage collection and wear-leveling.…”

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 98%

“…Therefore, some recent works are related to that direction. Want et al [81] proposed to eliminate inter-block disturbance by means of creating a physical distance between neighboring logical blocks. On the contrary, Chang et al [22] proposed a new life cycle of physical block to avoid writing pages whose adjacent pages currently contain valid data so as to reduce intra-block disturbance.…”

Section: B Program Disturbance Problemmentioning

confidence: 99%

“…In particular, big block [76], [22] and program disturbance [22], [81] are two critical issues that should be considered for garbage collection and wear-leveling. In the following sections, we will discuss the impact of these two problems on performing garbage collection or wear-leveling respectively in Section IV-A and Section IV-B.…”

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 99%

“…In contrast, more recent designs were based on static wear-leveling (SWL) [13], [19], [71], [79], which proactively move the static or cold (i.e., infrequently-updated) data so as to prevent any static or cold data from staying in the same block for long. This paper is motivated in providing a versatile survey of stateof-the-art garbage collection and wear-leveling designs, as well as an investigation on the development trends of future flash memory storage devices that incorporate triple-level-cell (TLC) flash memory [69] or even 3D flash memory [6], [12], [27], [76], [81], [82]. Here, the garbage collection issue is focused because the garbage collection might dramatically degrade the worst-case response time of write requests by several orders of magnitude, due to the excessive and unbounded overheads of live page copying in garbage collection 1 .…”

Section: Introductionmentioning

confidence: 99%

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Garbage collection and wear leveling for flash memory: Past and future

Yang

Chang

Tsao

et al. 2014

2014 International Conference on Smart Computing

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Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in nonvolatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious writeonce property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

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Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 98%

Section: B Program Disturbance Problemmentioning

confidence: 99%

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Garbage collection and wear leveling for flash memory: Past and future

Yang

Chang

Tsao

et al. 2014

2014 International Conference on Smart Computing

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“…For each write request, FTL will handle the write request and allocate a physical page. It will search and update the mapping table stored in RAM or in flash (Lines [15][16][17][18]. Based on the mapping information, FTL will issue write operations to the MTD layer, and the MTD layer will write or update data in the flash memory chip (Line 19).…”

Section: Metadata Transparent Replicationmentioning

confidence: 99%

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

Wang

Huang

Shao

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.

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