3D Floorplanning with Thermal Vias

Wong, Eric; Lim, Sung Kyu

doi:10.1109/date.2006.243773

Cited by 43 publications

(6 citation statements)

References 24 publications

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“…They also keep temperatures under 52°C (versus 90°C without FCAs), which is 4% more than the maximum in [6]. Both the IR-drop reduction and cooling are achieved with no TSV area overhead compared to [5] and [6].…”

Section: A Evaluation Of Ir-drop Reduction Using Fcasmentioning

confidence: 98%

“…In this context, methodologies were proposed to manage the thermal aspect of 3D MPSoCs in early floorplanning stages [13]. In particular, the insertion of thermal TSVs improves the heat extraction in 3D MPSoCs [6]. Nonetheless, using thermal TSVs has a high area overhead of 47% for a maximal temperature drop of only 38%.…”

Section: Related Work a 3d Integration Trends And Challengesmentioning

confidence: 99%

“…This phenomenon, referred to as IR-drop, manifests with local V DD drops that result in slower transitions of the affected gates and lead to timing violations [5]. In this context, many techniques have been proposed to improve heat dissipation and minimize IRdrop in 3D MPSoCs, by increasing the number of thermal [6] and Power and Ground (P/G) TSVs [5], respectively. However, these techniques generally involve a high TSV area overhead, which makes their implementation impractical and costly.…”

Section: Introductionmentioning

confidence: 99%

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A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Najibi

Levisse

Zapater

2019

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Integrated Flow Cell Array (FCA) technology promises to address the power delivery and heat dissipation challenges in three-dimensional Multi-Processor Systems-on-Chips (3D MPSoCs) by providing combined inter-tier liquid cooling and power generation capabilities. In this paper, we present for the first time a design framework to accurately model the temperature-aware power delivery network in 3D MPSoCs, and quantify the effects of FCAs on the voltage drop (IR-drop). This framework estimates the power generation variation along FCAs due to voltage and temperature, in the case of uniform and non-uniform powermaps from several real processor traces. Furthermore, we explore different 3D MPSoC configurations to quantify their power delivery requirements. Our results show that FCAs improve the IR-drop with respect to state-of-the-art design methods up to 53% and 30% for dies with a power consumption of 60W and 190W, respectively, while maintaining their peak temperatures below 52°C, and at no additional Through Silicon Via (TSV) area overhead. In addition, as the presence of high power density regions (hotspots) can decrease the FCAs IRdrop reduction by up to 21% with respect to the average value, we present a scalable TSV placement optimization methodology using the proposed framework. This methodology minimizes the IR-drop at hotspots and guarantees an optimal and uniform exploitation of the IR-drop reduction benefits of FCAs.Index Terms-3D multi-processor systems-on-chip, integrated flow cell arrays, liquid cooling, on-chip power generation, 3D power delivery network design

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Section: A Evaluation Of Ir-drop Reduction Using Fcasmentioning

confidence: 98%

Section: Related Work a 3d Integration Trends And Challengesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Najibi

Levisse

Zapater

2019

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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“…In this regard, several designtime solutions address the heat extraction problem in 3D ICs. Authors in [7] propose an algorithm to place thermal TSVs throughout the silicon bulk during floorplanning stages. Their approach, however, requires a significant area footprint and limits inter-layer communication bandwidth.…”

Section: Background On 3d Mpsoc Thermal and Power Managementmentioning

confidence: 99%

Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters

Najibi¹,

Levisse²,

Ansaloni³

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for threedimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technologies, which present very challenging power and thermal requirements. Indeed, FCAs effectively improve power delivery network (PDN) performance, particularly if switched capacitor (SC) converters are employed to decouple the flow cells and the systems-on-chip voltages, allowing each to operate at their optimal point. Nonetheless, the design of FCAbased solutions entails non-obvious considerations and trade-offs, stemming from their dual role in governing both the thermal and power delivery characteristics of 3D MPSoCs. Showcasing them in this paper, we explore multiple FCA design configurations and demonstrate that this technology can decrease the temperature of a heterogeneous 3D MPSoC by 78°C, and its total power consumption by 46%, compared to a high-performance cold-plate based liquid cooling solution. At the same time, FCAs enable up to 90% voltage drop recovery across dies, using SC converters occupying a small fraction of the chip area. Such outcomes provide an opportunity to boost 3D MPSoC computing performance by increasing the operating frequency of dies. Leveraging these results, we introduce a novel temperature and voltage-aware model predictive control (MPC) strategy that optimizes power efficiency during run-time. We achieve application-wide speedups of up to 16% on various machine learning (ML), data mining, and other high-performance benchmarks while keeping the 3D MPSoC temperature below 83°C and voltage drops below 5%.

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“…In 3D packages, thermal resistances and operating temperatures continue to increase. Conventional thermal management approaches include through-silicon-via optimization [34][35][36][37][38][39][40] and single-or two-phase cooling with microchannels [41][42][43][44][45][46].…”

Section: Introductionmentioning

confidence: 99%

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Kim

Ren

Yuksel³

et al. 2020

Journal of Electronic Packaging

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Thermal metamaterials exhibit thermal properties that do not exist in nature but can be rationally designed to offer unique capabilities of controlling heat transfer. Recent advances have demonstrated successful manipulation of conductive heat transfer and led to novel heat guiding structures such as thermal cloaks, concentrators, etc. These advances imply new opportunities to guide heat transfer in complex systems and new packaging approaches as related to thermal management of electronics. Such aspects are important, as trends of electronics packaging toward higher power, higher density, and 2.5D/3D integration are making thermal management even more challenging. While conventional cooling solutions based on large thermal-conductivity materials as well as heat pipes and heat exchangers may dissipate the heat from a source to a sink in a uniform manner, thermal metamaterials could help dissipate the heat in a deterministic manner and avoid thermal crosstalk and local hot spots. This paper reviews recent advances of thermal metamaterials that are potentially relevant to electronics packaging. While providing an overview of the state-of-the-art and critical 2.5D/3D-integrated packaging challenges, this paper also discusses the implications of thermal metamaterials for the future of electronic packaging thermal management. Thermal metamaterials could provide a solution to nontrivial thermal management challenges. Future research will need to take on the new challenges in implementing the thermal metamaterial designs in high-performance heterogeneous packages to continue to advance the state-of-the-art in electronics packaging.

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3D Floorplanning with Thermal Vias

Cited by 43 publications

References 24 publications

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays

Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

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