Decoupling capacitor (decap) is a popular means to reduce power supply noise in integrated circuits. Since the decaps are usually inserted in the whitespace of the device layer, decap management during the floorplanning stage is desirable. In this paper, we devise the Effective Decap Distance model to analyze how functional blocks are affected by non-neighboring decaps. In addition, we propose a generalized network flow-based algorithm to allocate the whitespace to the blocks and determine the oxide thicknesses for the decaps to be implemented in the whitespace. Experimental results show that our decap allocation and sizing methods can significantly reduce decap budget and leakage power with a small increase in area and wirelength when integrated into 2D and 3D floorplanners.

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3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is that their higher device density due to reduced footprint area leads to greater temperatures. Thermal vias are a potential solution to this problem. This paper presents a thermal via insertion algorithm that can be used to plan thermal via locations during floorplanning. The thermal via insertion algorithm relies on a new thermal analyzer based on random walk techniques. Experimental results show that, in many cases, considering thermal vias during floorplanning stages can significantly reduce the temperature of a 3D circuit.

Abstract-Three-dimensional (3-D) packaging via system-onpackage (SOP) is a viable alternative to system-on-chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this article, we present the first physical design algorithms for thermal and power supply noise-aware 3-D placement and crosstalk-aware 3-D global routing. Existing approaches consider the thermal distribution, power supply noise, and crosstalk issues as an afterthought, which may require an expensive cooling scheme, more decoupling capacitors (=decap), and additional routing layers. Our goal is to overcome this problem with our thermal/decap/crosstalk-aware 3-D layout automation tools. The traditional design objectives such as performance, area, wirelength, and via are considered simultaneously to ensure high quality results. The related experimental results demonstrate the effectiveness of our approaches.Index Terms-Crosstalk, mixed-signal CAD, placement and routing, power supply noise, system-on-package (SOP), thermal distribution, three-dimensional (3-D) packaging.

Abstract-The increased component density of a 3D SystemOn-Package (SOP) exacerbates the thermal hotspot problem. A popular choice to mitigate the thermal issues is thermal vias (t-vias) that are used to establish thermal paths from the core of an SOP package to the heat sinks. Another major problem with SOP integration is the power supply noise coupling among various mixed signal components constituting the system. In this case, decoupling capacitors (decaps) are inserted to provide the switching currents locally. The goal of our automatic 3D SOP component placement algorithm is to determine the x/y/z location of each component while minimizing the footprint area under thermal and power supply noise constraints. In general, t-vias and decaps are typically inserted in the white space in the placement, whereas the proximity of the t-vias and decaps to the target components determines their effectiveness. Hence, our component placer considers t-via and decap insertion during the early design stage, where the component location can be flexibly changed. Related experiments demonstrate the effectiveness of our approach.