3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

Then, Han Wui; Huang, Changyang; Krist, B.; Jun, Kimin; Lin, Kevin L.; Nidhi, Nitin; Michaelos, T.; Mueller, Brennen K.; Paul, R.; Peck, J.; Rachmady, W.; DasGupta, Sandeepan; Staines, D.; Talukdar, Tushar K.; Thomas, N.; Tronic, Tristan A.; Fischer, P.; Hafez, W.; Radosavljević, M.; Agababov, P.; Ban, I.; Bristol, Robert; Chandhok, Manish; Chouksey, S.; Holybee, B.

doi:10.1109/iedm19573.2019.8993583

Cited by 54 publications

(26 citation statements)

References 30 publications

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“…Although GaAs/InGaP HBTs grown on expensive GaAs substrates are already being used in PA for mobile phones [ 6 ], the heterogeneous integration of III–V compound semiconductors onto a 300 mm Si platform is one of the promising routes to enable hybrid III–V/CMOS technology for RF applications [ 7 , 8 ]. This will reduce cost, power losses, and chip footprint, while, at the same time, improving the flexibility of the circuit design, the overall system performance, and enabling the use of advanced 300 mm CMOS lithography and process capabilities for III–V device fabrication [ 8 , 9 ].…”

Section: Introductionmentioning

confidence: 99%

“…Although GaAs/InGaP HBTs grown on expensive GaAs substrates are already being used in PA for mobile phones [6], the heterogeneous integration of III-V compound semiconductors onto a 300 mm Si platform is one of the promising routes to enable hybrid III-V/CMOS technology for RF applications [7,8]. This will reduce cost, power losses, and chip footprint, while, at the same time, improving the flexibility of the circuit design, the overall system performance, and enabling the use of advanced 300 mm CMOS lithography and process capabilities for III-V device fabrication [8,9]. III-V nano-ridge engineering (NRE) is a unique method to monolithically co-integrate low defect density III-V material on Si, without the need for thick, strain-relaxed buffer layers on Si [6,10], or expensive (native) substrates followed by a complex transfer or bonding process [11].…”

Section: Introductionmentioning

confidence: 99%

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Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

et al. 2021

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Nano-ridge engineering (NRE) is a novel method to monolithically integrate III–V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106∙cm−2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices—consisting of several nano-ridges in parallel—were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III–V devices for hybrid III–V/CMOS technology for emerging RF applications.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

et al. 2021

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“…In 2019, high-K dielectric e-mode GaN based transistors fabricated on an HR Si (111) substrate with L g = 50 nm were reported. These devices showed excellent RF performance of f T = 190 GHz and f max = 300 GHz [108]. By introducing robust gate dielectric and GaN HEMTs with novel V-shaped gates were developed.…”

Section: Wide and Ultra-wide Bandgap Materials And Devicesmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called "Moore's law" in the past 60 years, and now has entered the post Moore's law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

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“…Figure 5 shows an example fabrication process flow of GaN devices. GaN devices with low RF loss, low buffer dispersion as well as good leakage blocking capability have been demonstrated by integrating the device on the Si platform based on the Au-free, Si CMOS compatible process [98,[101][102][103]. To enhance the functionality as well as the performance of the RF modules, various approaches to integrate CMOS and GaN devices have been developed [104,105].…”

Section: Cmos Compatible Process For Gan Hemtmentioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

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3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

Cited by 54 publications

References 30 publications

Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

Monolithic Integration of Nano-Ridge Engineered InGaP/GaAs HBTs on 300 mm Si Substrate

Recent progress of integrated circuits and optoelectronic chips

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

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