3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

Kw, Lee; Noriki, Akihiro; Kiyoyama, K.; Kanno, Shigenori; Kobayashi, R.; Jeong, Woo Cheol; Bea, J. C.; Fukushima, T.; Tanaka, Tetsu; Koyanagi, Mitsumasa

doi:10.1109/iedm.2009.5424305

Cited by 37 publications

(18 citation statements)

References 5 publications

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“…Fig. 19 shows a 3D optoelectronic LSI where an optoelectronic integrated circuit chip with Si photonic devices is stacked on CMOS chips [46]. The respective chip layers are vertically connected by both optical interconnections (TSPV, through-Si photonic via) and electrical interconnections (TSV, through-Si via).…”

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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“…The improvement of integration accuracy is being investigated by several research groups [4][5][6][7][8][9]. Attempting to improve the alignment accuracy of the FCB method through increasing the resolution of the alignment stage motion and increasing the magnification of the IR image camera is not sufficient for high-precision bonding.…”

Section: Introductionmentioning

confidence: 98%

“…Generally, the post-bond accuracy of presently commercialized FCB machines has been limited to the range of 2 μm -5 μm, because of unavoidable effects such as thermal-induced misalignment caused by thermal expansion mismatching between the bonding chip and substrate, and by horizontal shifting of the press tool due to the shear force generated from the large down force during pressing. For emerging demands, such in photonics-electronics convergence system technology -PECST (Figure 1), the optical performance of a system is highly dependent on the coupling efficiency which is mainly affected by assembly deviations [1][2][3][4]. Therefore, the integration accuracy of the FCB approach needs to be improved significantly in order to realize low power consumption, highspeed, high-performance photonics-electronics systems.…”

mentioning

confidence: 99%

“…For emerging demands, such in photonics-electronics convergence system technology -PECST (Figure 1), the optical performance of a system is highly dependent on the coupling efficiency which is mainly affected by assembly deviations [1][2][3][4]. Therefore, the integration accuracy of the FCB approach needs to be improved significantly in order to realize low power consumption, highspeed, high-performance photonics-electronics systems.The improvement of integration accuracy is being investigated by several research groups [4][5][6][7][8][9]. Attempting to improve the alignment accuracy of the FCB method through increasing the resolution of the alignment stage motion and increasing the magnification of the IR image camera is not sufficient for high-precision bonding.…”

mentioning

confidence: 99%

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Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications

Thanh

Suzuki

Kato

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Thermosonic flip-chip bonding (TS-FCB) is known as a technique suitable for low-temperature bonding and has been used in many integration applications. In this paper, a modified TS-FCB based on microbumps and concave pads, is presented. Electroplated Cu microbumps, and etched invertpyramid-shape bonding pads are used to enhance the bonding accuracy of the conventional TS-FCB technique. Experimental validation of the bonding approach is conducted. Reliable bonds, with significant increase in the post-bond accuracy, i.e. within 1 μm range in in-plane offsets, are obtained at 120 ºC using the proposed bonding approach. These achievements illustrate the ability to use this approach for highprecision low-temperature converging applications. IntroductionThe flip-chip bonding (FCB) with thermal compression method has been a promising technique for high density interconnection while only needing a simple process. Generally, the post-bond accuracy of presently commercialized FCB machines has been limited to the range of 2 μm -5 μm, because of unavoidable effects such as thermal-induced misalignment caused by thermal expansion mismatching between the bonding chip and substrate, and by horizontal shifting of the press tool due to the shear force generated from the large down force during pressing. For emerging demands, such in photonics-electronics convergence system technology -PECST (Figure 1), the optical performance of a system is highly dependent on the coupling efficiency which is mainly affected by assembly deviations [1][2][3][4]. Therefore, the integration accuracy of the FCB approach needs to be improved significantly in order to realize low power consumption, highspeed, high-performance photonics-electronics systems.The improvement of integration accuracy is being investigated by several research groups [4][5][6][7][8][9]. Attempting to improve the alignment accuracy of the FCB method through increasing the resolution of the alignment stage motion and increasing the magnification of the IR image camera is not sufficient for high-precision bonding. Additionally, highprecision alignment systems have high costs, as well as very long process times. The key point to achieve high-precision bonding results is to maintain the alignment of the chip and the substrate during the bonding process [10][11][12].In our work, the integration accuracy is effectively improved by means of maintaining the alignment between the chip and substrate during bonding, aiming at sub-micron range precision, at an acceptably low temperature. In our previous works, we have succeeded in making reliable 10 μm-

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“…3D-LSI has great advantages, such as parallel processing, high packaging density, low power consumption, short global wiring length, and high-speed operation [2]- [6]. However, it has some problems to be solved for practical applications.…”

Section: Introductionmentioning

confidence: 99%

Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI

Kino

Bea

Murugesan

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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A three-dimensional (3-D) LSI has many lots of throughSi vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first time, we investigated impacts of the static and dynamic local bending on MOSFET characteristics using a novel test structure. Introduction3-D LSI consisting of vertically stacked several thin Si chips with many TSVs and metal microbumps have attracted much attention as a promising evolution system that enhances LSI performance [1]. 3D-LSI has great advantages, such as parallel processing, high packaging density, low power consumption, short global wiring length, and high-speed operation [2]-[6]. However, it has some problems to be solved for practical applications. In particular, great interest in electrical is mechanical reliability issues are increasing among 3-D LSI researchers. Conventional 3-D LSIs consist of five key technologies, as shown in Fig. 1 [7]- [11]. TSVs and metal microbumps electrically connect between upper and lower Si chips. The thinning of the Si chips leads to a thinner LSI package and a shorter TSV. A shorter TSV makes it possible to decrease parasitic capacitance, electric resistance, and process cost. Chip alignment technology is required to have alignment accuracy less than 1 μm to realize high-density TSV interconnects. It is also necessary to fill an adhesive material called underfill among layers to increase mechanical strength. The organic adhesive surrounds metal microbumps between upper and lower thinned Si chips.

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3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

Cited by 37 publications

References 5 publications

Recent progress in 3D integration technology

Recent progress in 3D integration technology

Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications

Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI

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