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We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed. IntroductionThe parallel processing by using a multi-processor system is the most promising way to achieve high-overall speed and efficient throughput in computation. It is well known that a shared memory is very useful to build the high-performance parallel processor system with simple configuration and architecture. However, the conventional system with a shared memory has the drawback that only limited number of processors can be connected to a shared memory due to the bus-bottleneck problem. This is because the processors are connected to the shared memory through a common bus in the conventional system as shown in Fig. 1 (a). Therefore, the date stored in the memory cannot be simultaneously shared among several processors due to bus-bottleneck. Such bus-bottleneck problem can be solved by using a multiport memory with many readlwrite ports which act as a real shared memory. However, it is not easy to realize a high-speed multiport memory with many read/write ports using the conventional technology. Then, we have proposed a new three-dimensional (3D) multiport memory with many read/write ports which acts as a real shared memory [I]. We can realize a high-performance parallel processor system by using such new multiport memory as shown in Fig. 1 (b). In order to achieve such 3D multiport memory that we call "3D shared memory", we have developed a new 3D integration technology based on wafer stacking method [2-51 and fabricated the 3D shared memory test chip which consists of three memory layers.

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