Future system-on-silicon LSI chips

Koyanagi, Mitsumasa; Kurino, Hiroyuki; Lee, Kang Wook; Sakuma, Katsuyuki; Miyakawa, Nobuaki; Itani, Hikotaro

doi:10.1109/40.710867

Cited by 329 publications

(115 citation statements)

References 3 publications

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“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

“…However through-Si vias (TSVs) were not used in these 3D test chips. Then a 3D integration technology using through-Si vias (TSVs) suitable for the volume production has been proposed [6,7,8]. Several thinned LSI chips with TSVs and metal microbumps are vertically stacked in this 3D integration technology as shown in Fig.…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

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Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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“…This defining feature of 3-D ICs offers unique opportunities for highly heterogeneous and sophisticated systems [8]. This heterogeneity, however, greatly complicates the interconnect design process within a multi-plane system, as potential design methodologies need to manage the diverse interconnect impedance characteristics and process variations caused by the different fabrication processes and technologies employed in the multiple physical planes [9].…”

Section: Introductionmentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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“…This defining feature of 3-D ICs offers unique opportunities for highly heterogeneous and sophisticated systems [19], [20]. A vast pool of applications such as medical, wireless communications, military, and low-cost consumer products, exists for vertical integration, as the proximity of the system components caused by the third dimension is suitable for either the high performance or low power ends of the SoC application space [114].…”

Section: Introductionmentioning

confidence: 99%