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Abstract-Memristors are novel devices, which can be used in applications such as memory, logic, and neuromorphic systems. A memristor offers several advantages to existing applications: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristors have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristor model is presented -TEAM, ThrEshold Adaptive Memristor model. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.

Memristors are novel electrical devices used for a variety of applications including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to the nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this paper, some applications require voltage controlled memristors to operate properly. In this paper, the Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage controlled memristors. The VTEAM model extends the previously proposed TEAM model, which describes current-controlled memristors. The VTEAM model has similar advantages to the TEAM model: it is simple, general, and flexible and can characterize different voltage controlled memristors. The VTEAM model is accurate (below 1.5% in terms of relative root mean squared error) and computationally efficient as compared to existing memristor models and experimental results describing different memristive technologies.

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Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described, the clock distribution networks of specific industrial circuits are surveyed, and future trends are discussed.