Clock distribution networks in synchronous digital integrated circuits

Abstract

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described, the clock distribution networks of specific industrial circuits are surveyed, and future trends are discussed.

Implementation of an Asynchronous Micro-controlleron the Commercial FPGA

“…Because the asynchronous circuit does not have any globalized control signal inherently, optimization and control path design strategy could not be same with synchronous circuit one [15]- [18].…”

Design and implementation of clock network for nanometer FPGA

“…Clock network is a dedicated network for distributing multiple clock signals to every logic module in a system, playing a crucial part to the chip's performance [1,2,3,4]. Hence the design of clock network becomes the utmost issue.…”

“…With regard to the general clock network design, recent researches can be classified into several categories. Symmetric structures such as Htree [1] and X-tree [5] can minimize clock skew even achieve zero-skew clock routing. But the absolutely symmetrical structure is extremely sensitive to the process variation.…”

Skew variability in 3-D ICs with multiple clock domains

“…There is a plethora of methods to manage the excessive clock skew in the design phase [2]. Careful physical design, however, does not eliminate the undesirable skew since the unwanted skew can be also introduced in the fabrication phase.…”