Three-dimensional shared memory fabricated using wafer stacking technology

Lee, K.W.; Nakamura, Tomoji; Ono, Takahito; Yamada, Yusuke; Mizukusa, T.; Hashimoto, Hiroyuki; Park, K.T.; Kurino, Hiroyuki; Koyanagi, Mitsumasa

doi:10.1109/iedm.2000.904284

Cited by 108 publications

(42 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

View full text Add to dashboard Cite

3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

show abstract

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Several kinds of 3D packages such as wafer-to-wafer bonding technologies [1] have been applied to things such as image sensor chips [2] and shared memory. [3] A chip-to-wafer technology has also been actively investigated. [4] This paper reports on a SiP (chip-to-wafer) that was fabricated using wafer-level chip-size package (W-CSP) technologies.…”

Section: Introductionmentioning

confidence: 99%

Multi-Chip Module Fabricated by W-CSP Method using Excimer Laser Via-Hole Formation and Cu Plating

Suzuki¹,

Tamura²,

Fujisaki³

et al. 2009

Transactions of The Japan Institute of Electronics Packaging

View full text Add to dashboard Cite

Recently high-density packaging technologies have been in strong demand in an effort to realize the ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmentally-friendly packaging. The purpose of this study is to propose a fabrication method for a multichip module system using W-CSP technology. In this study, we fabricated a two-chip module with W-CSP using an excimer laser to form via-holes and electro-plating to fill the via-holes. This study has two main new technologies: one is new via-hole formation using an excimer laser that makes small (30 μm diameter) and deep (50 and 100 μm) via-holes, with a micro-lens array used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. The second new technology is new copper electroplating techniques to fill the via-holes which have same diameter (30 μm) and different depths (50 and 100 μm) by controlling additives and agitating conditions. In this study, we fabricated a two-chip module, and both chips were covered by resin simultaneously. The second chip, whose thickness was 50 μm, was mounted on a wafer (first chip) after the first chip had completed the wafer process. The second chip was thinned and mounted by die attachment film (DAF). Next, the mounted chips were spin-coater with polyimide or epoxy resin about 100 μm in thickness. Two types of via-hole with different depths, 50 and 100 μm, were formed by excimer laser to connect the wafer and mounted chip pads. Both types of via-hole had a diameter of about 30 μm. After via-hole formation, seed layers, sputtered Ti and Cu films, are necessary for subsequent copper electro-deposition. Using microscopy measurement, the seed layers were seen to be uniformly formed from the top to the bottom of the via-hole.Using a general mixture of additives, brightener, leveler, and suppressor, the via-holes were completely filled. By controlling the suppressor effect, the 100 μm deep via-holes were perfectly filled with the copper electroplating. Both mechanical agitation and current density are effective to ensure via-hole filling and optimization of these two factors is very important in filling via-holes. Moreover, an additional electroless copper seed layer to increase conductivity near the bottom of the via-hole is also effective to suppress voids there. Finally, the conductivities between the first and second chips were confirmed for the multi-chip module fabricated using W-CSP with excimer laser and copper electro-plating.

show abstract

“…Several kinds of 3D packages such as wafer-to-wafer bonding technologies [1] have been applied to things such as image sensor chips [2] and shared memory. [3] A chip-to-wafer technology has also been actively investigated. [4] This paper reports on SiP (chip-to-wafer) that has been fabricated using waferlevel chip size package (W-CSP) technologies.…”

Section: Introductionmentioning

confidence: 99%

Via-Hole Formation by Excimer Laser and Filling by Electro-Plating

Suzuki¹,

Tamura²,

Fujisaki³

et al. 2008

Transactions of The Japan Institute of Electronics Packaging

View full text Add to dashboard Cite

A multi-chip module (MCM) was fabricated using an excimer laser driller and electro-plating. This method contributes to the interconnection properties of the MCM. First, a second chip with a thickness of 50 μm was mounted on a wafer that had been created by a wafer process, and polyimide with a thickness of about 100 μm was applied by a spin-coater to cover the mounted chips. Two types of via-holes, with depths of 50 and 100 μm, were formed by the excimer laser to connect the wafer and mounted chip pads. The excimer laser driller with a micro-lens array formed two types of via with diameters of about 30 μm simultaneously. Damage caused by the excimer laser irradiation was examined by direct laser irradiation of the FET transistor gate. Properties of the FET transistor did not change even after 500 pulses of 400 mJ/ cm 2 which is sufficient for via-hole formation. A micro-lens array was designed to shorten the via-hole formation time.After via-hole formation, a seed-layer of sputtered Ti and Cu films were necessary, followed by copper electro-deposition.Microscopy measurements confirmed that the seed-layers were uniformly formed from top to bottom of the via-hole. Generally the mixture of additives to complete the via-hole filling consists of brightener, leveler, and a suppressor. By controlling the leveler concentration, a via-hole with a diameter of 30 μm and a depth of 100 μm was perfectly filled by copper electroplating. In this way the multi-chip module was created by wafer-level chip size technologies (W-CSP) using an excimer laser driller.

show abstract

Three-dimensional shared memory fabricated using wafer stacking technology

Cited by 108 publications

References 2 publications

Recent progress in 3D integration technology

Recent progress in 3D integration technology

Multi-Chip Module Fabricated by W-CSP Method using Excimer Laser Via-Hole Formation and Cu Plating

Via-Hole Formation by Excimer Laser and Filling by Electro-Plating

Contact Info

Product

Resources

About