3D IC design partitioning for temperature rise minimization

Abstract

Due to the low thermal conductivities of dielectrics between active layers, there is a strong demand to minimize the temperature rise of three-dimensional integrated circuits (3D ICs). In this paper, we demonstrate that, in the design of 3D ICs, different design partitioning results often lead to different amounts of temperature rise. However, to the best of our knowledge, no attention has been paid to the problem of design partitioning for temperature rise minimization. Based on that observation, we propose an integer linear programming (ILP) approach to find a design partitioning solution in which the amount of temperature rise is minimized. Compared with the previous work (that does not take the temperature rise into account), experimental results show that our approach can reduce 13.60% temperature rise without any extra overhead.

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

“…With the progress in EDA tools in the last few years, the temperature rise of 3D IC can be minimized by design path finding and partitioning. 74,75 It was proposed to manage dissipative heat using thermal aware floor plan and placement. 76 However, thermal aware floorplan and placement may not be enough, which leads to the uses of signal and power network TSVs for thermal dissipation.…”