3D Monolithic Stacked 1T1R cells using Monolayer MoS&lt;inf&gt;2&lt;/inf&gt; FET and hBN RRAM Fabricated at Low (150°C) Temperature

Wang, Ching-Hua; McClellan, Connor J.; Shi, Yuanyuan; Zheng, Xin; Chen, Victoria; Lanza, Mario; Pop, Eric; Wong, H.-S. Philip

doi:10.1109/iedm.2018.8614495

Cited by 41 publications

(38 citation statements)

References 8 publications

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“…This is because these 2D insulators ideally also have no dangling bonds and can adhere to the 2D semiconductors by van der Waals attraction, resulting in a minimized amount of interface states. Moreover, h‐BN dielectric stacks have shown a very high reliability when exposed to electrical fields, and have been already implemented in FETs, resistive switching based nonvolatile memories, and electronic synapses . Other wide bandgap 2D layered materials that may adhere to the 2D semiconducting channel by van der Waals attraction may also work well as gate dielectric in 2D‐FETs.…”

Section: Device Fabricationmentioning

confidence: 99%

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

Illarionov

Yalon

et al. 2019

Adv Funct Materials

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The continuous miniaturization of field effect transistors (FETs) dictated by Moore's law has enabled continuous enhancement of their performance during the last four decades, allowing the fabrication of more powerful electronic products (e.g., computers and phones). However, as the size of FETs currently approaches interatomic distances, a general performance stagnation is expected, and new strategies to continue the performance enhancement trend are being thoroughly investigated. Among them, the use of 2D semiconducting materials as channels in FETs has raised a lot of interest in both academia and industry. However, after 15 years of intense research on 2D materials, there remain important limitations preventing their integration in solid-state microelectronic devices. In this work, the main methods developed to fabricate FETs with 2D semiconducting channels are presented, and their scalability and compatibility with the requirements imposed by the semiconductor industry are discussed. The key factors that determine the performance of FETs with 2D semiconducting channels are carefully analyzed, and some recommendations to engineer them are proposed. This report presents a pathway for the integration of 2D semiconducting materials in FETs, and therefore, it may become a useful guide for materials scientists and engineers working in this field.

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Section: Device Fabricationmentioning

confidence: 99%

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

Illarionov

Yalon

et al. 2019

Adv Funct Materials

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“…This work demonstrated a novel compact memory cell that integrates the functionalities of both transistor and RRAM into a single "smart" device, which is uniquely enabled by vdW materials, leveraging CVD grown lateral graphene-WS 2graphene heterostructure as well as vertical heterostructured h-BN/WS 2 and h-BN/graphene stack configurations, thereby justifying the designation of "0.5T0.5R" memory cell. This hybrid structure reduces the device count of a conventional 1T1R cell by half and is shown to exhibit extraordinary performance, energy efficiency, and compactness, as benchmarked against previous reports on vdW-material based memory cells/devices [38]- [43] in Table I. Specifically, sub-10 ns SET/RESET, 0.07 pJ/bit energy consumption, and 12 μm 2 cell footprint are achieved, which represents a great leap in advancing RRAM and "1T1R" memory technology.…”

Section: Discussionmentioning

confidence: 69%

“…10(b). Although these numbers are better than previous reports on 2-D materials-based 1T1R memory cells [38], [39], more follow-up efforts are needed to derive further improvements. It is noteworthy that the transistor component introduces one more knob (the gate voltage, V g ) to control the memory cell resistance.…”

Section: B Rram Componentmentioning

confidence: 63%

0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures

Zhang

Yeh

Cao

et al. 2021

IEEE Trans. Electron Devices

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Conventional designs of the extensively studied resistive-random access-memory (RRAM) cell involve one transistor and one RRAM-"1T1R," i.e., two separate devices thereby constraining its integration density. In this work, we overcome this longstanding limitation by experimentally demonstrating a novel memory architecture that combines the 1T and 1R into a single hybrid device by uniquely leveraging both lateral and vertical van der Waals (vdW) heterostructures. This ultracompact device, which can be considered as a "0.5T0.5R" memory cell, reduces the device count by half-the first of its kind in RRAM technology history, and simultaneously allows higher lateral as well as vertical (3-D) integration density w.r.t. the conventional 1T1R architecture. The unique "smart" device that can retain information after power is turned off is structurally designed by utilizing a shared graphene edge-contact and resistively switchable hexagonal boron nitride (h-BN) insulator. Aided by design optimization, record performance (<10 ns switching-speed), energy-(∼0.07 pJ/bit), and area-efficiency (smallest footprint among all reported vdW-material-based RRAM memory units), as well as great retention (10 6 s) and endurance (>1000), benchmarked against current vdWmaterial-based RRAM devices, have been achieved by this 0.5T0.5R memory cell. Moreover, the RRAM's fine tunability with ultrashort pulsewidth, pulse amplitude, and gate voltage, enables synaptic plasticity and makes it an integrated three-terminal RRAM with considerable potential for neuromorphic and in-memory computing applications.

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“…As illustrated in left panel of Figure 5g, oxygen vacancies in active layer are accumulated near graphene edge, since the activation energy of O 2− diffusion in graphene electrode (0.15-0.8 eV) is much lower than that of TiN electrode (0.98-2.1 eV). By using 2D semiconductor as transistor channel material and 2D insulator as memristive material, respectively, researchers have experimentally demonstrated 3D monolithically integrated one-transistor oneresistor (1T1R) cells, [124] and shown potential of 2D materials in future high-density integration of memristive devices. This assumption has been justified by the results of spatially resolved Raman spectrum.…”

Section: Wwwadvelectronicmatdementioning

confidence: 99%

2D Layered Materials for Memristive and Neuromorphic Applications

Wang

Meng

et al. 2019

Adv Elect Materials

102

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demonstrated that the memristive devices exhibit many promising features, [3][4][5][6][7][8] such as non-volatility, high speed switching, high endurance, high-density integration, CMOS-compatible fabrication, and so on. These features make them ideal candidates for applications in memory devices, [3,5,9] in-memory computing, [3,[10][11][12] and edge computing. [13,14] The working principle of the TMOs-based memristive devices relies on ion drift or diffusion, which resembles motion of ions in the biological neurons and synapses. The ionic motions exhibit dynamic behaviors. Thus, the memristive devices can be used to emulate the synaptic plasticity [15] and neurons. [16][17][18] Compared to traditional silicon synapses [19][20][21] and neurons [22,23] requiring complex circuits, such emerging memristive devices have compact structures and enhanced func-

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3D Monolithic Stacked 1T1R cells using Monolayer MoS<inf>2</inf> FET and hBN RRAM Fabricated at Low (150°C) Temperature

Cited by 41 publications

References 8 publications

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures

2D Layered Materials for Memristive and Neuromorphic Applications

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