3D Multi-chip Integration with System on Integrated Chips (SoIC™)

Hu, Clark; Chen, M.F.; Chiou, W.C.; Yu, Douglas

doi:10.23919/vlsit.2019.8776486

Cited by 53 publications

(15 citation statements)

References 3 publications

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“…Considerations on performance for various chip stacking and interconnect methods were conducted for 3D IC chip stacking in parallel. Five chip stacking and interconnect methods were compared [50]. It was found that the face-toface chip stacking and shortest interconnect can increase the speed and bandwidth than the other four methods.…”

Section: Summary and Analysismentioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS Image Sensors (CIS) for different functions such as visible light detection, Single Photon Avalanche Photodiode (SPAD) for low light detection, rolling shutter and global shutter, and depth sensing and Light Detection And Ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultra-high-density interconnect manufacturability is also highlighted.

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Section: Summary and Analysismentioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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“…The energy per bit overhead for F2F is reported as 0.013 pJ at nominal voltage [14]. The energy overhead of F2B over F2F is reported as 12X [36]. Hence, to incorporate an average case impact of vertical interconnect energy on the overall DRAM access energy of a 4-tier system, 1.35 pJ per byte (one F2F, one F2B) is added to all DRAM transfers of 3D accelerator configurations.…”

Section: A Power and Performance Analysis Flowmentioning

confidence: 99%

“…The delay overhead of 3D F2F vertical interconnect can be "5 ps at nominal voltage [14]. The energy overhead of a F2B connection (through TSVs) over F2F is 3.2X [36]. Hence, to incorporate a worst-case impact of the vertical interconnect delay on the frequency of a 4-tier system, 42 ps (two F2F, two F2B) is added to the cycle time (1/freq) of 3D accelerator configurations.…”

Section: A Power and Performance Analysis Flowmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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ML accelerators have a broad spectrum of usecases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on Processing Element (PE) array dimensions and SRAM buffer sizes. 3D integration packs more compute or memory in the same 2D footprint, which can be utilized to build more powerful or energyefficient accelerators. However, 3D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3D systolic accelerators. Using this framework, different 3D-partitioned accelerator configurations are proposed and evaluated. The 3D-stacked accelerator designs are modeled using hybrid wafer bonding technique with a 1.44 µm pitch of 3D connection. Results show that different partitioning of the systolic array and SRAM buffers in a 4-tier 3D configuration can lead to either 1.1-3.9X latency reduction or 1-3X energy reduction compared to the baseline design of the same 2D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3D across benchmarks can be limited to 6°C.

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“…They are used in high-end electronic devices, such as complementary metal oxide semiconductor (CMOS) image sensors [ 1 ] and high bandwidth memory (HBM) [ 2 ]. To fabricate high-performance computing chips, a three-dimensional integrated circuit (3D IC) technique is employed [ 3 , 4 ]. However, challenges still exist in 3D IC packaging [ 5 ], for instance, with the reliability of interconnects [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Shie

Hsu

et al. 2021

Materials

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The failure mechanisms of Cu–Cu bumps under thermal cycling test (TCT) were investigated. The resistance change of Cu–Cu bumps in chip corners was less than 20% after 1000 thermal cycles. Many cracks were found at the center of the bonding interface, assumed to be a result of weak grain boundaries. Finite element analysis (FEA) was performed to simulate the stress distribution under thermal cycling. The results show that the maximum stress was located close to the Cu redistribution lines (RDLs). With the TiW adhesion layer between the Cu–Cu bumps and RDLs, the bonding strength was strong enough to sustain the thermal stress. Additionally, the middle of the Cu–Cu bumps was subjected to tension. Some triple junctions with zig-zag grain boundaries after TCT were observed. From the pre-existing tiny voids at the bonding interface, cracks might initiate and propagate along the weak bonding interface. In order to avoid such failures, a postannealing bonding process was adopted to completely eliminate the bonding interface of Cu–Cu bumps. This study delivers a deep understanding of the thermal cycling reliability of Cu–Cu hybrid joints.

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3D Multi-chip Integration with System on Integrated Chips (SoIC™)

Cited by 53 publications

References 3 publications

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

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