2021
DOI: 10.3390/ma14195522
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Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Abstract: The failure mechanisms of Cu–Cu bumps under thermal cycling test (TCT) were investigated. The resistance change of Cu–Cu bumps in chip corners was less than 20% after 1000 thermal cycles. Many cracks were found at the center of the bonding interface, assumed to be a result of weak grain boundaries. Finite element analysis (FEA) was performed to simulate the stress distribution under thermal cycling. The results show that the maximum stress was located close to the Cu redistribution lines (RDLs). With the TiW a… Show more

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Cited by 30 publications
(11 citation statements)
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“…The schematic diagram of fabrication processes is shown in Figure 2 . Detailed processes can be referred to in our previous study [ 12 ]. The cross-sections of the joints were then characterized using focused ion beam (DB-FIB, Field Electron and Ion Company, Hillsboro, OR, USA), and the surface roughness ( R q ) was examined by an atomic force microscope (AFM, Bruker Dimension Edge and Dimension Icon, Bruker Company, Billerica, MA, USA).…”
Section: Experimental and Simulation Sectionmentioning
confidence: 99%
See 1 more Smart Citation
“…The schematic diagram of fabrication processes is shown in Figure 2 . Detailed processes can be referred to in our previous study [ 12 ]. The cross-sections of the joints were then characterized using focused ion beam (DB-FIB, Field Electron and Ion Company, Hillsboro, OR, USA), and the surface roughness ( R q ) was examined by an atomic force microscope (AFM, Bruker Dimension Edge and Dimension Icon, Bruker Company, Billerica, MA, USA).…”
Section: Experimental and Simulation Sectionmentioning
confidence: 99%
“…Although <111> crystal orientation is beneficial for direct bonding, a relatively high density of voids at the center of the bonding interface was still observed after a temperature cycling test without an applied force [ 12 ]. Various voids originally exist at metal surfaces and then move along grain boundaries to the center of the bonding interface due to stress gradients [ 13 , 14 , 15 ].…”
Section: Introductionmentioning
confidence: 99%
“…In the semiconductor industry, copper (Cu) is considered as the most commonly used interconnect for fan-out wafer level packaging thanks to its superior electrical and thermal conductivity [ 1 , 2 , 3 , 4 , 5 , 6 ]. In order to enhance the computing performance of electronic devices, logic chips and interconnects are required to scale down significantly [ 7 , 8 , 9 ]. During operation, Cu lines are subjected to a high current density resulting in severe failures related to electromigration (EM), stress migration, and Joule heating [ 10 , 11 , 12 ].…”
Section: Introductionmentioning
confidence: 99%
“…The sample for the EM test is shown in Figure 1. A top die was bon die through instant Cu-Cu direct bonding [18,31]. The method of electr winned Cu (nt-Cu) [32,33] was adopted to fabricate nt-Cu microbumps be lumnar grains have a (111) surface for low-thermal-budget bonding [15 chanical properties [34][35][36][37].…”
Section: Introductionmentioning
confidence: 99%