3D Multi-gate Transistors: Concept, Operation, and Fabrication

Shehata, Nader; Gaber, Abdel-Rahman; Naguib, Ahmed; Selmy, Ayman E.; Hassan, Hossam M.; Shoeer, Ibrahim; Ahmadien, Omar; Nabeel, Rewan

doi:10.17265/2328-2223/2015.01.001

Cited by 8 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Park et al 34 presented their experimental findings on a multichannel double‐gate MOSFET. The concept, operation, and fabrication feasibility of 3D‐multi‐gate transistors were discussed by Shehata et al 35 Emam et al 36 conducted experimental investigations into the performance of a graded channel MOSFET. Larson et al 37 conducted experimental studies on SB MOSFETs.…”

Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

This study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2, VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivatives gm2 and gm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

show abstract

Section: Device Structure Simulation and Fabricationmentioning

confidence: 99%

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…Park et al [24] has experimentally reported a multichannel tri‐gate MOSFET. Shehata et al [25] has discussed the concept, operation, and fabrication feasibility of 3D‐multi gate transistors. Emam et al [26] has experimentally investigated the noise performance in a graded channel MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Analytical investigation of a triple surrounding gate germanium source metal–oxide–semiconductor field‐effect transistor with step graded channel for biosensing applications

Das

Rewari

Kanaujia

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

This paper proposes a compact analytical model and comprehensively investigates the biosensing performance of a novel dielectric modulated triple surrounding gate germanium source metal–oxide–semiconductor field‐effect transistor with a step graded channel. Solving the 2D Poisson's equation yields an analytical expression of threshold voltage, channel potential, drain current and sub threshold swing. The sensitivity variation in the biosensor has been thoroughly studied by varying different device parameters to investigate its biosensing performance. Graded doping in channel offers enhanced sensitivity than a non‐graded doped channel when the doping of the channel is more near the drain end than source end which is due to stronger electric field and gate capacitance. Effect of fill‐in factor for different biomolecules on the sensitivity has been thoroughly discussed. Different analytical results show an excellent agreement with the simulations done on SILVACO ATLAS TCAD simulator.

show abstract

“…These fields often vary spatially as can be seen, e.g., for modern transistors that have 3D architectures with different doping levels-and hence depletion region widths-in various directions. [6,7] Moreover, the lateral dimensions of these doped regions are becoming increasingly small. [6] In batteries, for example, potentials that limit or induce electron or ion transport, drop over the so-called Debye-length, extending over nanometers to hundreds of nanometers.…”

Section: Introductionmentioning

confidence: 99%

Measuring Spatially‐Resolved Potential Drops at Semiconductor Hetero‐Interfaces Using 4D‐STEM

et al. 2023

View full text Add to dashboard Cite

Characterizing long‐range electric fields and built‐in potentials in functional materials at nano to micrometer scales is of supreme importance for optimizing devices, e.g., the functionality of semiconductor hetero‐structures or battery materials is determined by the electric fields established at interfaces which can also vary spatially. In this study, momentum‐resolved four‐dimensional scanning transmission electron microscopy (4D‐STEM) is proposed for the quantification of these potentials and the optimization steps required to reach quantitative agreement with simulations for the GaAs/AlAs hetero‐junction model system are shown. Using STEM the differences in the mean inner potentials (∆MIP) of two materials forming an interface and resulting dynamic diffraction effects have to be considered. This study shows that the measurement quality is significantly improved by precession, energy filtering and a off‐zone‐axis alignment of the specimen. Complementary simulations yielding a ∆MIP of 1.3 V confirm that the potential drop due to charge transfer at the intrinsic interface is ≈0.1 V, in agreement with experimental and theoretical values found in literture. These results show the feasibility of accurately measuring built‐in potentials across hetero‐interfaces of real device structures and its promising application for more complex interfaces of other polycrystalline materials on the nanometer scale.

show abstract

3D Multi-gate Transistors: Concept, Operation, and Fabrication

Cited by 8 publications

References 17 publications

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Analytical investigation of a triple surrounding gate germanium source metal–oxide–semiconductor field‐effect transistor with step graded channel for biosensing applications

Measuring Spatially‐Resolved Potential Drops at Semiconductor Hetero‐Interfaces Using 4D‐STEM

Contact Info

Product

Resources

About