3D multi-stacking of thin dies based on TSV and micro-inserts interconnections

Souriau, Jean-Charles; Castagné, Laetitia; Liotard, Jean-Luc; Inal, Karim; Mazuir, J.; Texier, F. Le; Fresquet, Gilles; Varvara, Maxime; Launay, N.; Dubois, Beatrice; Malia, Thierry

doi:10.1109/ectc.2012.6248965

Cited by 5 publications

(7 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, micro-inserts and interlocking bump structures (Sec. 2.1) have been assembled in this way [28,29]. The thermocompression method does not require the reflow process and has been used to create tiny, fine-pitch interconnections [13].…”

Section: Bonding Withmentioning

confidence: 99%

“…3). Souriau et al used micro-insert interconnection technology in their chip-to-wafer stacking study [29]. In that process, a matrix of micro-inserts made of Ni was inserted in the soft NiSn material, which was formed on the corresponding location on the wafer (or on other dies).…”

Section: Introductionmentioning

confidence: 99%

“…Various deposition methods are also commonly used. For example, in Souriau et al's micro-inserts approach, the Ni and NiSn layers were formed by the electroplated chemical deposition method on a Ti/Cu seed layer, while the seed layer was deposited by physical vapor deposition [29].…”

Section: Introductionmentioning

confidence: 99%

“…Cross section image showing interlocking Sn/Cu bumps (left) and a Cu planar bump with TSVs (right)[28] Image of fabricated micro-inserts[29] …”

mentioning

confidence: 99%

See 3 more Smart Citations

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

View full text Add to dashboard Cite

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

show abstract

Section: Bonding Withmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Cross section image showing interlocking Sn/Cu bumps (left) and a Cu planar bump with TSVs (right)[28] Image of fabricated micro-inserts[29] …”

mentioning

confidence: 99%

See 2 more Smart Citations

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

View full text Add to dashboard Cite

show abstract

“…Figure 14 shows results obtained on a test vehicle using micro-inserts for interconnection 6 . A Kelvin bump pattern which includes a matrix of 16 micro-inserts has been used for electrical resistance measurement 7 .…”

Section: Die Stackingmentioning

confidence: 99%

Optical Characterization and Defect inspection for 3D stacked IC technology

Fresquet¹,

Piel²

2014

International Symposium on Microelectronics

Self Cite

View full text Add to dashboard Cite

Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes. To increase the development speed, it is a big advantage that metrology and defect inspection need to be present on the same platform and a flexible tool, with multi sensors, to be more versatile facing the different step of the process will be presented in this paper As 3D IC devices utilize TSVs for direct interconnect, the depth, top and bottom CD (critical diameter) of such TSVs with a diameter as small as 5 μm with a high aspect ratio is characterized. During wafer temporary bounding, which is an handling technique that allows wafer thinning with a thickness of less than 100 μm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass. After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined. After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed. Post CMP process control will be addressed by full field interferometry especially prior Copper to Copper direct bonding. Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate. In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow characterizing specifically and with an excellent sensitivity the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing will be detailed and results will be presented to illustrate the possibilities of this inspection by microscopy.

show abstract