3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Khan, N.; Yu, Hong; Pin, Tan Siow; Ho, Soon Wee; Su, Nandar; Hnin, Wai Yin; Kripesh, V.; Pinjala,; Lau, John H.; Chuan, Toh Kok

doi:10.1109/ectc.2009.5074157

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…Fig. 2 shows a typical chip configuration with embedded MFHS in the literature, in which the fluid is supplied through a single inlet from the top of the stack [8], [10]. References [8] and [10] demonstrated the cooling of a four-tier and a two-tier stack with total power dissipation of 390 and 200 W, respectively.…”

Section: B Embedded Microfluidic Heat Sink In the Literaturementioning

confidence: 99%

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Cooling is a significant challenge for highperformance and high-power 3-D ICs. In this paper, tier-specific microfluidic cooling technology is proposed and experimentally evaluated in a 3-D stack. Different stacking scenarios are experimentally evaluated including: 1) a memory-on-processor stack; 2) a processor-on-processor stack with equal power dissipation; 3) a processor-on-processor stack with different power dissipations; and 4) a two-tier 3-D stack with each tier containing four cores along the flow direction. Compared with conventional microfluidic cooling, the tier-specific cooling is shown to reduce the pumping power by 37.5% by preventing overcooling when an operating temperature is specified. The results are benchmarked with an air-cooled heat sink. The impact of the lateral thermal gradient along the flow direction on the electrical performances, including leakage power and clock frequency, is analyzed.Index Terms-3-D IC, leakage power, microchannel heat sink, micropin-fin (MPF) heat sink, multicore processors.

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Section: B Embedded Microfluidic Heat Sink In the Literaturementioning

confidence: 99%

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Power electronic equipments, computers, high energy batteries used in hybrid and electric vehicles where water was used as working fluid. In computers, fans were used to cir- The heat must be rejected from microchips to sustain a temperature within tolerable limits less than 100 • C. Currently, stacks of integrated electrical circuits can be cooled by water using a system designed and built by a research team Khan et al [28] from the A STAR Institute of Microelectronics and Nanyang University in Singapore.…”

Section: Subscriptsmentioning

confidence: 99%

Experimental Investigation on Heat Transfer Enhancement from a Channel Mounted with Staggered Blocks

et al. 2015

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The present work experimentally investigates heat transfer enhancement from a channel mounted with staggered blocks. The effect of the geometrical parameters, such as the square and circular shapes of the blocks and the ratio of the centre to centre spacing between the blocks (L x /L y ratio) along the stream-wise direction and transverse direction of flow, has been investigated. Experiments were conducted using the newly developed experimental setup for Reynolds number ranging from 100 to 500 based on the hydraulic diameter and the average velocity of flow through the channel. The heat input values varied from 100 to 300 W with a step of 50 W, and water was used as working fluid. The results suggest that the variation of the Reynolds number significantly influenced the heat transfer enhancement compared with other geometrical parameters. The squareshaped block imposed greater impact on the heat transfer than the circular blocks. An increase in the heat transfer was observed while increasing the L x /L y ratios from 1.5 to 2.5 for the square blocks, whereas it was reduced for the circular blocks.

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“…As with many other new technologies, TSVs still face many critical issues. In the development of TSVs, the following must be noted and understood (Lau, 2009a(Lau, , b, c, 2010a(Lau, , b, 2011Lau et al, 2010a, b;Lau and Tang, 2009;Yu et al, 2008aYu et al, , b, 2009aTang et al, 2010;Chen et al, 2008c;Premachandran et al, 2008;Zhang et al, 2009a, b;Hoe et al, 2009;Choi et al, 2009;Vempati et al, 2009;Khan et al, 2008Khan et al, , 2009Sekhar et al, 2008;Ho et al, 2008;Selvanayagam et al, 2009;Sekiguchi et al, 2006;Takahashi and Sekiguchi, 2006;Garrou et al, 2009;Ramm et al, 2008;Andry et al, 2008;Knickerbocker et al, 2008;Kumagai et al, 2008;Sunohara et al, 2008;Lee et al, 2007;Matsuo et al, 2000;Wong et al, 2006;Beica et al, 2008;Wolf et al, 2008;Henry et al, 2008):…”

Section: Critical Issues Of Tsvmentioning

confidence: 99%

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Lau

2011

Microelectronics International

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283

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Purpose -The purpose of this paper is to focus on through-silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented. Design/methodology/approach -This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for highpower, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) format with excellent thermal management. Findings -A generic, low-cost and thermal-enhanced 3D IC integration SiP with a passive interposer has been proposed for high-performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high-power chips on top and low-power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to "dig" holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (.99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high-power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper-filled TSV interposer and the high-and low-power chips are recommended to reduce creep damage of the lead-free microbump solder joints and prolong their lives. Originality/value -The paper's findings will be very useful to the electronic industry.

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3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

Cited by 15 publications

References 7 publications

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Experimental Investigation on Heat Transfer Enhancement from a Channel Mounted with Staggered Blocks

Overview and outlook of through‐silicon via (TSV) and 3D integrations

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