3D Sensor application with open through silicon via technology

Abstract

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for More than Moore solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven open TSV technology on the basis of a 0.35m CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35m CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxi de layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35m CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250m and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the op

Electromigration reliability of open TSV structures

“…1. The geometrical dimensions given in [1] are used. Here, the tungsten, shown in red, forms an hollow cylinder closed on the bottom side.…”

“…Interconnections for 3D integrated circuits, though, include components not used in planar 2D architectures, such as through silicon vias (TSVs). Open TSVs introduced in [1] are a TSV concept in which the cylindrical structure is coated, rather than entirely filled with a conducting metal. Fig.…”

Intrinsic stress analysis of tungsten-lined open TSVs

“…The presence of a void in the middle of the TSV allows for material expansion, avoiding the reliability concerns related to copper pumping which is common to filled TSVs [4]. However, an open TSV requires more wafer area and quite complex processing techniques [3]. The processing steps to manufacture an open TSV include deep reactive ion etching (DRIE) as well as several deposition steps, usually performed with a form of chemical vapor deposition (CVD) [3].…”

“…Several studies deal with the reliability and performance of filled copper TSVs [2] as well as open tungsten-lined TSVs [3]. Open TSVs are desired when the stress build-up due to material thermal expansion is a concern.…”

Scanning acoustic gigahertz microscopy for metrology applications in three-dimensional integration technologies

“…The results presented here include a case study employing acoustic microscopy on samples representing an innovative 3-D sensor integration concept. 4 In this approach, an application-optimized sensor layer is processed on a specific wafer substrate. The sensor is vertically connected to a readout circuitry chip produced in standard CMOS technology by Si direct wafer bonding.…”