A modified high-pressure, stopped-flow apparatus has been developed to enable kinetic experiments to be monitored spectrophotometrically to 200 MPa, with efficient mixing of the reactant solutions. This apparatus is compact, relatively inexpensive to construct, and the solutions are only exposed to inert materials, such as Kel-F, Teflon, quartz (low-pressure windows), and glass or Viton. The drive-syringe pistons are propelled by a step motor housed on top of the stopped-flow unit inside the pressure vessel, resulting in a dead time for the system of ∼10 ms at 25 °C.

In this work, we present a significant step toward in vivo ophthalmic optical coherence tomography and angiography on a photonic integrated chip. The diffraction gratings used in spectral-domain optical coherence tomography can be replaced by photonic integrated circuits comprising an arrayed waveguide grating. Two arrayed waveguide grating designs with 256 channels were tested, which enabled the first chip-based optical coherence tomography and angiography in vivo three-dimensional human retinal measurements. Design 1 supports a bandwidth of 22 nm, with which a sensitivity of up to 91 dB (830 µW) and an axial resolution of 10.7 µm was measured. Design 2 supports a bandwidth of 48 nm, with which a sensitivity of 90 dB (480 µW) and an axial resolution of 6.5 µm was measured. The silicon nitride-based integrated optical waveguides were fabricated with a fully CMOS-compatible process, which allows their monolithic co-integration on top of an optoelectronic silicon chip. As a benchmark for chip-based optical coherence tomography, tomograms generated by a commercially available clinical spectral-domain optical coherence tomography system were compared to those acquired with on-chip gratings. The similarities in the tomograms demonstrate the significant clinical potential for further integration of optical coherence tomography on a chip system.

In this work we present a detailed analysis of individual loss mechanisms in silicon nitride partial Euler bends at a wavelength of 850 nm. This structure optimizes the transmission through small radii optical waveguide bends. The partial Euler bend geometry balances losses arising from the transition from the straight to the bend waveguide mode, and radiative losses of the bend waveguide mode. Numerical analyses are presented for 45-degree bends commonly employed in S-bend configurations to create lateral offsets, as well as 90-and 180-degree bends. Additionally, 90-degree partial Euler bends were fabricated on a silicon nitride photonic platform to experimentally complement the theoretical findings. The optimized waveguide bends allow for a reduced effective radius without increasing the total bend loss and, thus, enable a higher component density in photonic integrated circuits.

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for More than Moore solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven open TSV technology on the basis of a 0.35m CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35m CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxi de layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35m CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250m and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the op

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