3D Si‐on‐Si stack packaging

Abstract

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

Contact resistance and shear strength of the solder joints formed using Cu bumps capped with Sn or Ag/Sn layer

“…It can minimize the interconnection length, and enables ultrafine pitch interconnections. [2][3][4] The chip to chip bonding process using Cu bump with Sn-Ag alloy capping layer was developed by the Association of Super-Advanced Electronic Technologies. 4,5 This method was preconditioned with the Ar sputtering cleaning to reduce oxide layers and contaminations of bump surfaces.…”