Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Jang, Dong Min; Ryu, Chunghyun; Lee, Kwang Yong; Cho, Byeong-Hoon; Kim, Joungho; Oh, Tae-Sung; Lee, Won Jong; Yu, Jin

doi:10.1109/ectc.2007.373897

Cited by 129 publications

(52 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The electrical characteristics of the TSVs are of primary importance in 3-D ICs and are considerably different from the horizontal interconnect segments [44], as described by recent electrical models [45]. This situation is due to the structure of these interconnects and the diverse technologies, such as CMOS and SOI, that can exist in a 3-D system.…”

Section: A Vertical Interconnectsmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

View full text Add to dashboard Cite

show abstract

Section: A Vertical Interconnectsmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

View full text Add to dashboard Cite

show abstract

“…To illustrate the design process a seven level architecture is presented in figure 7, where the break point is shown between levels 3 and 4. For this study the communication is realized with Through Silicon Via (TSV) and electrical characterization of TSVs was performed based on the approach from [15]. The electrical model and parasitic components for each TSV was realized using the electrical model of TSV interconnect presented in [15].…”

Section: -Dimensional Tree-based Multilevel Fpga Designmentioning

confidence: 99%

“…For this study the communication is realized with Through Silicon Via (TSV) and electrical characterization of TSVs was performed based on the approach from [15]. The electrical model and parasitic components for each TSV was realized using the electrical model of TSV interconnect presented in [15]. The interconnect length of levels above the break point level for 3D Tree-based FPGA timing characterization was extracted from the re-designed floorplan shown in figure 7.…”

Section: -Dimensional Tree-based Multilevel Fpga Designmentioning

confidence: 99%

See 1 more Smart Citation

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

Pangracious

Marrakchi²,

Amouri

et al. 2013

Lecture Notes in Computer Science

View full text Add to dashboard Cite

. Performance analysis and optimization of high density tree-based 3d multilevel FPGA. Abstract. A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development of a Tree-based multilevel interconnect network is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to redistribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers discussed. The impact of of Through Silicon Vias and performance improvement on 3D Tree-based FPGA analyzed and also an optimized physical design technology leveraging on TSV, Thermal-TSV (TTSV), and thermal analysis are presented. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and a performance improvement of 53% recorded in our place and route experiments.

show abstract

“…The method based on the equivalent thermal circuits is one of the effective methods in recent researches, in which the thermal transient response can be analyzed accurately and quickly by extracting the thermal resistance, thermal capacity and building the equivalent thermal circuit model [8,9]. Lau J.H.…”

Section: Introductionmentioning

confidence: 99%

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

Li¹,

Zou²,

Shang³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The transmission performance of TSV considering the effect of electronic-thermal coupling is an new challenge in three dimension integrated circuit. This paper presents the thermal equivalent circuit (TEC) model of the TSV, and discussed the thermal equivalent parameters for TSV. Si layer is equivalent to transmission line according to its thermal characteristic. Thermal transient response (TTR) of TSV considering electronic-thermal coupling effects are proposed, iteration flow electronic-thermal coupling for TSV is analyzed. Furthermore, the influences of TTR are investigated with the noncoupling and considering coupling for TSV. Finally, the relationship among temperature, thickness of SiO 2 , radius of via and frequency of excitation source are addressed, which are verified by the simulation.

show abstract

Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Cited by 129 publications

References 9 publications

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

Contact Info

Product

Resources

About