3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond

Kim, Do-Won; Li, Hong Yu; Chang, K. W.; Loh, Woon Leng; Chong, Ser Choong; Cai, Hong; Surya, Batara

doi:10.1109/ectc.2018.00129

Cited by 8 publications

(4 citation statements)

References 7 publications

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“…The drawbacks in this case are the design area flexibility needed for surface optical coupling with 3D integrated PICs (increased real estate for optical connectivity) and the thermal management required where the heat generated by the EICs implies functional changes in the PIC (with temperature-sensitive components, such as ring resonators − ). An electronic–photonic integrated circuit (EPIC) approach has been proposed, in which a test vehicle consisting of a silicon-on-insulator (SOI) die with through silicon vias (TSVs) flip-chip bonded on a silicon interposer demonstrated an insertion loss of <3.5 dB up to 50 GHz . A high-density 3D electronic–photonic integration with through-oxide technology where the SOI wafer is oxide bonded face-to-face with the CMOS wafer has also demonstrated a full 5 Gb/s chip-to-chip link over a 100 m single mode optical fiber.…”

Section: Electronic–photonic Co-packagingmentioning

confidence: 99%

“…An electronic−photonic integrated circuit (EPIC) approach has been proposed, in which a test vehicle consisting of a silicon-on-insulator (SOI) die with through silicon vias (TSVs) flip-chip bonded on a silicon interposer demonstrated an insertion loss of <3.5 dB up to 50 GHz. 101 A high-density 3D electronic−photonic integration with through-oxide technology where the SOI wafer is oxide bonded face-to-face with the CMOS wafer has also demonstrated a full 5 Gb/s chip-to-chip link over a 100 m single mode optical fiber. The electrical and optical energy consumption in this case is 560 fJ/bit and 4.2 pJ/bit respectively.…”

Section: ■ Electronic−photonic Co-packagingmentioning

confidence: 99%

See 1 more Smart Citation

Integrated Photonics Packaging: Challenges and Opportunities

et al. 2022

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Packaging of photonic integrated circuit (PIC) chips is an essential and critical step before they can be integrated into functional optoelectronic systems. Photonic packaging is however often a major barrier impeding scalable deployment of PIC technologies given its high cost and limited throughput. This perspective addresses the technical challenges and discusses promising strategies and research directions to overcome the "packaging bottleneck".

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Section: Electronic–photonic Co-packagingmentioning

confidence: 99%

Section: ■ Electronic−photonic Co-packagingmentioning

confidence: 99%

Integrated Photonics Packaging: Challenges and Opportunities

et al. 2022

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“…Common methods for interconnecting these two devices are wire bonding or bump bonding [11]. Generally, bump bonding has better packaging performance than wire bonding [12], which is useful and available in the current packaging structure [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

RF Interconnection Design of Bump Bonding with a Dislocation Package Structure towards Electro-Optic Modulation Applications

Peng,

Wang,

Wang

et al. 2023

Photonics

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Bonding technology can be an important component of packaging for photonic chips, such as electro-optic (EO) modulators and other active function devices. In general, an EO modulator chip can achieve a broader 3 dB EO bandwidth than its packaging device, as the packaging design and structure can technically limit modulation performance. Recently, bump bonding has been shown to be a good candidate for the EO interconnection technique, which has a higher transmission bandwidth than wire bonding. In this article, we propose a design for radio frequency (RF) interconnection of bump bonding with a dislocation packaging (BBDP) structure. Through simulation calculations and analysis, the proposed BBDP structure shows a 3 dB transmission bandwidth of approximately 145 GHz, which is 52.6% better than one using optimized wire-bonding structures (95 GHz). The proposed packaging structure presents an important alternative method for ultrahigh speed optical modulation applications.

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“…This study will focus on the SiPho interposer process integration and technology development. Previous studies have reported on SiPho interposer, Through Silicon Via (TSV) and wave-guide or Micro Ring Resonator (MRR) co-integration [4][5][6][7][8][9] however, none of them has described a full operating system. The following paper will first briefly introduce the POPSTAR system components and architecture followed by the design and technological stack of the corresponding SiPho interposer [3].…”

Section: Introductionmentioning

confidence: 99%

Process Integration of Photonic Interposer for Chiplet-based 3D Systems

Saint-Patrice

Malhouitre

Assous

et al. 2023

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

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To overpass the bandwidth and the latency limitations of electrical links, the next breakthrough in high performance computing integration will eventually come through photonic technology and Optical Network-on-Chip (ONoC). This work introduces a global architecture of an ONoC and reports the detail integration and fabrication on the 200 mm Leti's platform of a Si photonic interposer on SOI wafers. Active photonic circuit operating at 1310 nm wavelength, 12 µm diameter 100 µm height Through Silicon Via (TSV) middle process, four metal layers Back-End Of Line (BEOL) with µ-pillars and backside redistribution layer with thermal cavity above heaters have been successfully achieved. Morphological characterizations as crosssections assess the process developments and integration results. Optical propagation losses measured on Rib and Deep Rib structures and insertion losses on Single Polarization Grating Couplers (SPGC) structures both at the end of the active photonic and after TSV / BEOL processes show no deviation. The TSV middle resistance is evaluated below 22 mΩ with a yield greater than 95 %. Finally, all individual process blocks required for the functional ONoC system, especially Ring Modulators is discussed regarding their successful optimized co-integration.

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3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond

Cited by 8 publications

References 7 publications

Integrated Photonics Packaging: Challenges and Opportunities

Integrated Photonics Packaging: Challenges and Opportunities

RF Interconnection Design of Bump Bonding with a Dislocation Package Structure towards Electro-Optic Modulation Applications

Process Integration of Photonic Interposer for Chiplet-based 3D Systems

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