4.6dB/5.5dB NF and 6.5dB/21.5dB gain 2 stages and 6 stages 76-81GHz LNAs for radar application in 28nm RF CMOS FD-SOI

2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

et al. 2022

Self Cite

This paper presents an innovative x3 sub-sampling frequency downconverter for converting signals around 77 GHz from a 26 GHz LO signal. With a LO frequency divided by 3 this topology allows drastic simplifications on the receiver's LO distribution chain. The sub-sampling mixer operation principle is described and implemented with 28-nm FD-SOI CMOS technology. Simulation results show a 1dB input-referred compression power (ICP1dB) of +3 dBm and a 14.4 dB Noise Figure (NF) with a -2.5 dB conversion gain. The mixer's LO signal shaper consumption is 36 mW on a 1.2V supply while the passive mixer core doesn't require DC power.

Section: Implementation and Simulation Resultsmentioning

confidence: 99%

A ×3 Sub-Sampling Mixer for a 77 GHz Automotive Radar Receiver in 28 nm FD-SOI CMOS Technology

Flete

2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

et al. 2022

Self Cite

“…As stand-alone passive mixers are not presented in the literature related to CMOS 77 GHz radar receivers, a meaningful comparison between this sampling mixer and other existing solutions is a bit difficult. The proposed sampling mixer has been implemented with a variation of the LNA presented in [8] in a 77 GHz front-end (LNA + mixer). As a result, a proper comparison with the state of the art can be provided.…”

Section: Implementation and Measurement Resultsmentioning

confidence: 99%

A New 77 GHz Sampling Mixer in 28-nm FD-SOI CMOS Technology for Automotive Radar application

Flete

2022 IEEE/MTT-S International Microwave Symposium - IMS 2022

et al. 2022

This paper presents a low-IF sampling mixer topology based on a new pulse shaper and designed for automotive radar application. The sampling mixer operation principle is described. Then an original pulse shaper topology convenient for a 77 GHz sampling operation is proposed and implemented in 28-nm FD-SOI CMOS technology. Measurement results show a 1dB input-referred compression power (ICP1dB) of +6.7 dBm and a 9.1 dB Noise Figure (NF) with a conversion gain of -0.7 dB. The power consumption of the mixer is 10 mW on a 1V supply.

A Low-Loss 77 GHz Sub-Sampling Passive Mixer Integrated in a 28-nm CMOS Radar Receiver

Flete¹,

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

et al. 2022

This paper demonstrates that using sub-sampling mixer topology can be the right choice to implement a millimeter-wave (mmW) receiver. In a 77 GHz radar receiver, it allows to reduce the burden of a 77 GHz LO distribution chain, in term of area and consumption, while preserving RF performances. Demonstration is done from two topologies of ×3 sub-sampling mixers implemented in 28-nm FD-SOI CMOS technology. The best proposed passive mixer exhibits a -2.1 dB conversion gain (Gcv), a 1dB input-referred compression power (ICP1dB) of +3.5 dBm, and a 16.8 dB Single Side Band Noise Figure (NFSSB). The mixer LO signal shaping consumption is 32 mW on a 1.2 V supply while the passive mixer core does not require any DC power.