A microreplicated (MR) pad with regulated long-range order surface pore-asperity patterns is used for the buff polish step in a 3-platen W-CMP process for 14 nm replacement metal gate (RMG) and trench salicide (TS) planarization. This new pad requires no diamond tip conditioner and can last up to 2000 wafer passes with highly repeatable removal rates, while maintaining low and consistent defects and within-wafer uniformity. The MR pad also provides unique benefits of mitigating within-die non-uniformity as demonstrated by gate electrical conductance tests and confirmed by physical thickness measurement through cross-sectional TEM. In addition, topography-driven defects are reduced significantly. The mechanisms responsible for the unique performance of MR pads will be elucidated and the significance of this new CMP pad technology will be discussed. Chemical-mechanical planarization (CMP) has become a pivotal manufacturing process for new integration schemes of semiconductor devices ever since its invention in the 1980s. From the implementation of Cu interconnects early on to the realization of field-effect transistors (FinFET) for 22 nm technology and beyond, CMP is the process that enables leading-edge device performance. With shrinking feature size for advanced technology nodes, however, the planarity requirements for CMP are tightened down to the order of several nanometers across the entire 300 mm wafer. Meanwhile, the tolerance for non-uniformity reduces to only a few percent within-die, within-wafer, and wafer-towafer for 14 nm technology nodes and above. As a consequence, advances in CMP equipment and consumables are urgently need in order to meet such stringent planarity and uniformity criteria.Conventional approaches to within-wafer CMP planarity and uniformity control such as the optimization of polish pressure, platen/carrier rotation, slurry flow, pad conditioning, slurry components, and so forth have become the standard practice at the end-user level. Coupled with advances in equipment technologies, the above approaches provide wafer to sub-wafer level thickness and planarity correction. When combined with metrology-based advanced process control (APC), they can help reduce wafer-to-wafer variation as well. Recent progress in RIE technology also enables across-wafer thickness correction die by die and assists CMP to achieve nano-scale within-wafer uniformity.1,2 However, there is still a lack of effective method to mitigate one of the longest lasting major challenges of CMP, the pattern dependency, 3-5 which would give rise to within-die nonuniformity (WIDNU). As illustrated in Fig. 1, pattern dependency arises when the initial difference in pattern density among various structures creates a global step height variation, due to the difference in removal rates before the local patterns are planarized. In the case of tungsten replacement metal gate (W-RMG) CMP, such within-die gate height variation will translate to drift in gate resistance and threshold voltage across different devices, compromising t...