4-phase resettable quasi-adiabatic flip-flops and sequential circuit design

Maheshwari, Sachin; Bartlett, V.A.; Kale, I.

doi:10.1109/prime.2016.7519498

Cited by 6 publications

(10 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the past, various examples like 16-bit CLA [9], 8-bit multiplier [10], mode-10 counter [3] and 2-bit twisted ring counter [7] has been implemented to show the comparison between different adiabatic logic families and CMOS design in terms of energy efficiency. The existing designs lacked to give a comparison which encompasses performance issues among adiabatic logic families using different power-clocking scheme [12].…”

Section: Design Example and Performance Resultsmentioning

confidence: 99%

“…Whereas, the transistor N3 is turned 'OFF' disconnecting the path of node 'outR' from the power supply. A more detailed description of its nonadiabatic losses can be found in [7], [10]. As shown in Fig 6 (a), the main part of CPAL evaluation tree (N5-N8) is designed using the pass-transistors which are connected to the gates of the nMOS transistors (N3, N4) representing the PFAL buffer.…”

Section: Positive Feedback Adiabatic Logic (Pfal)mentioning

confidence: 99%

“…Secondly, due to the extra input pin in the multiplexer which leads to an overhead in the routing of the complementary and non-complementary signals. The power-clock generator can be implemented using a stepwise charging circuit [11] but for the ease of simulation a trapezoidal wave, ramping from 0V to 1.8V is taken [7]. We use minimum sized transistors for all the designs based on TSMC 180nm CMOS technology.…”

Section: Adiabatic Flip-flopsmentioning

confidence: 99%

“…It is also called 2N-2N2P logic [5]. The Basic operation and working of IECRL are described in [6], [7]. The IECRL resettable buffer circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The EACRL provides a stable output, due to the duplicate evaluation network. A detailed operation and working can be found in [7], [9].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Maheshwari

Bartlett

Kale

2017

2017 European Conference on Circuit Theory and Design (ECCTD)

Self Cite

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk

show abstract

Section: Design Example and Performance Resultsmentioning

confidence: 99%

Section: Positive Feedback Adiabatic Logic (Pfal)mentioning

confidence: 99%

Section: Adiabatic Flip-flopsmentioning

confidence: 99%

“…It is also called 2N-2N2P logic [5]. The Basic operation and working of IECRL are described in [6], [7]. The IECRL resettable buffer circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The EACRL provides a stable output, due to the duplicate evaluation network. A detailed operation and working can be found in [7], [9].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Maheshwari

Bartlett

Kale

2017

2017 European Conference on Circuit Theory and Design (ECCTD)

Self Cite

View full text Add to dashboard Cite

show abstract

Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC and Embedded Applications

Samanta¹,

Mahapatra

Mal

2022

Studies in Computational Intelligence

View full text Add to dashboard Cite

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

Self Cite

View full text Add to dashboard Cite

The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

show abstract

4-phase resettable quasi-adiabatic flip-flops and sequential circuit design

Cited by 6 publications

References 10 publications

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC and Embedded Applications

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Contact Info

Product

Resources

About