Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Maheshwari, Sachin; Bartlett, V.A.; Kale, I.

doi:10.1109/ecctd.2017.8093257

Cited by 8 publications

(6 citation statements)

References 11 publications

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“…Depending on the 'CD' and 'CU' signals, the counter either count down or up. The boolean expression for the 3-bit up-down counter is given in [17] and its corresponding circuit diagram is given in Fig. 9.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This behavior forms a pipeline, processing one input and one output at every power-clock phase. Recent work on the performance comparison of the adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking scheme [16], [17] and the powerclock generator [12]- [14] has contributed and distant a myth on the adiabatic logic capability of providing an energy efficient alternative to non-adiabatic logic. Based on the comparison results, the 4-phase adiabatic system is the most promising in terms of performance and energy requirement compared to single and 2-phase power-clocking adiabatic logic scheme [17].…”

Section: Adiabatic Logic Technique and Encoding Of Trapezoidal Waveformsmentioning

confidence: 99%

“…3 shows the VHDL simulation for generating the adiabatic power-clock signal. The approach can also be easily used for single-phase and 2-phase adiabatic logic techniques, although it will not be straightforward in the case of 2-phase adiabatic logic due to its long idle period [17].…”

Section: Adiabatic Logic Technique and Encoding Of Trapezoidal Waveformsmentioning

confidence: 99%

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VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

Maheshwari

Bartlett

Kale

2018

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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In comparison to conventional CMOS (nonadiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit updown counter, as a design example that demonstrates the practicality of the proposed approach.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Adiabatic Logic Technique and Encoding Of Trapezoidal Waveformsmentioning

confidence: 99%

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VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

Maheshwari

Bartlett

Kale

2018

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…This behaviour forms a pipeline, such that at every powerclock phase one input and one output is processed. Recently proposed work on the performance comparison of the adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking scheme [28], [30] and on the powerclock generator [14], [15] have contributed to the knowledge base and dispelled a myth on the adiabatic logic capability of providing an energy efficient alternative to the non-adiabatic logic. In [28], [30] the authors show that the 4-phase adiabatic system is the most promising in terms of performance and energy requirement in comparison to the single and 2-phase adiabatic logic designs.…”

Section: Fig 2 Pfal Buffermentioning

confidence: 99%

“…a smart card) and the rising energy density due to the technology shrinkage, energy-efficiency has become a major concern in the design of large and complex systems. A circuit technique, known as "Adiabatic Logic" based on the CMOS technology, has the potential for low energy operation albeit at some cost in terms of performance speed [1]- [3], [10]- [13], [17]- [30]. Thus, making it a worthy choice for smart card application.…”

Section: Introductionmentioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

Sanadhya¹,

Sharma²

2023

Springer Tracts in Electrical and Electronics Engineering

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Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers

Cited by 8 publications

References 11 publications

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

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