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The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

Shift register is one of the important components in any digital circuit. By improving the performance of shift register, one can improvise the whole system performance. Shift registers are the basic memory units and data transfer devices in IoT applications. The efficacy of computing devices depends on the performance of arithmetic circuits, including shift registers. Adiabatic logic has been proposed as anew computing platform to develop power‐efficient IoT devices. This paper presents low power adiabatic shift registers. The design of shift registers uses D flipflop, based on DC‐DB PFAL (direct‐current diode based positive feedback adiabatic logic). Performance parameters of the presented circuits are analyzed for transistor count, power dissipation, latency, and PDP (power delay product). Simulations are run for all the presented circuits at 180nm and 45nm technology nodes. It is found that the proposed parallel in parallel out shift register (PIPO) design outperforms with the improvement in PDP as 53%, 53%, and 57% compared to theserial in serial out (SISO), serial in parallel out (SIPO), and parallel inserial out (PISO) shift registers respectively at 100MHz and 45 nm technology node. Further, the proposed PIPO shift register shows improved performance than the other designs in the literature.