40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86&amp;#x2013;64 core

Golden, M.; Arekapudi, S.; Vinh, James

doi:10.1109/isscc.2011.5746228

Cited by 19 publications

(11 citation statements)

References 3 publications

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“…These buses are {2 (read)+1 (write)}×5 (unit) = 15 tracks of 8-bit wire bundles. These wires are routed in an upper layer, whose pitch is twice as thick as that in the lower layers used for RAMs [11] and switches. Thus, 15 × 2 = 30 tracks can be used within this width for the RAMs and switches.…”

Section: -Bit Slicementioning

confidence: 99%

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.

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Section: -Bit Slicementioning

confidence: 99%

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

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show abstract

“…Yet, because we do not implement the whole NoSQ infrastructure and since we did not tune the Distance predictor to handle memory dependency predictions well, we assume the presence of enough sources in the scheduler, which is optimistic but not unrealistic. For instance, AMD Bulldozer's scheduler supports 4 sources per instruction [17], which would be enough for both additional dependencies.…”

Section: Validationmentioning

confidence: 99%

Cost effective physical register sharing

Seznec

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Sharing a physical register between several instructions is needed to implement several microarchitectural optimizations. However, register sharing requires modifications to the register reclaiming process: Committing a single instruction does not guarantee that the physical register allocated to the previous mapping of its architectural destination register is freeable anymore. Consequently, a form of register reference counting must be implemented.While such mechanisms (e.g., dependency matrix, per register counters) have been described in the literature, we argue that they either require too much storage, or that they lengthen branch misprediction recovery by requiring sequential rollback. As an alternative, we present the Inflight Shared Register Buffer (ISRB), a new structure for register reference counting. The ISRB has low storage overhead and lends itself to checkpoint-based recovery schemes, therefore allowing fast recovery on pipeline flushes.We illustrate our scheme with Move Elimination (shortcircuiting moves) and an implementation of Speculative Memory Bypassing (short-circuiting store-load pairs) that makes use of a TAGE-like predictor to identify memory dependencies. We show that the whole potential of these two mechanisms can be achieved with a small register tracking structure.

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“…This is roughly two times fewer entries than Haswell's scheduler. Assuming a baseline CAM-like scheduler and 6/8 results per cycle, then each entry of the scheduler must provision 12/16 comparators for wakeup, assuming 2 operands per entry (consider that AMD Bulldozer's actually has up to 4 per entry [14]). The speculative window only requires as many comparators per entry as there are blocks fetched per cycle (granted that the comparators are bigger since we match 15 bits instead of [6][7][8].…”

Section: A Remark On Power and Energymentioning

confidence: 99%

BeBoP: A cost effective predictor infrastructure for superscalar value prediction

Seznec¹

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Up to recently, it was considered that a performance-effective implementation of Value Prediction (VP) would add tremendous complexity and power consumption in the pipeline, especially in the Out-of-Order engine and the predictor infrastructure.Despite recent progress in the field of Value Prediction, this remains partially true. Indeed, if the recent EOLE architecture proposition suggests that the OoO engine need not be altered to accommodate VP, complexity in the predictor infrastructure itself is still problematic. First, multiple predictions must be generated each cycle, but multi-ported structures should be avoided. Second, the predictor should be small enough to be considered for implementation, yet coverage must remain high enough to increase performance.To address these remaining concerns, we first propose a block-based value prediction scheme mimicking current instruction fetch mechanisms, BeBoP. It associates the predicted values with a fetch block rather than distinct instructions. Second, to remedy the storage issue, we present the Differential VTAGE predictor. This new tightly coupled hybrid predictor covers instructions predictable by both VTAGE and Stride-based value predictors, and its hardware cost and complexity can be made similar to those of a modern branch predictor. Third, we show that block-based value prediction allows to implement the checkpointing mechanism needed to provide D-VTAGE with last computed/predicted values at moderate cost.Overall, we establish that EOLE with a 32.8KB block-based D-VTAGE predictor and a 4-issue OoO engine can significantly outperform a baseline 6-issue superscalar processor, by up to 62.2% and 11.2% on average (gmean), on our benchmark set.

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40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86–64 core

Cited by 19 publications

References 3 publications

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Cost effective physical register sharing

BeBoP: A cost effective predictor infrastructure for superscalar value prediction

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