Cost effective physical register sharing

Abstract

Sharing a physical register between several instructions is needed to implement several microarchitectural optimizations. However, register sharing requires modifications to the register reclaiming process: Committing a single instruction does not guarantee that the physical register allocated to the previous mapping of its architectural destination register is freeable anymore. Consequently, a form of register reference counting must be implemented.While such mechanisms (e.g., dependency matrix, per register counters) have been described in the literature, we argue that they either require too much storage, or that they lengthen branch misprediction recovery by requiring sequential rollback. As an alternative, we present the Inflight Shared Register Buffer (ISRB), a new structure for register reference counting. The ISRB has low storage overhead and lends itself to checkpoint-based recovery schemes, therefore allowing fast recovery on pipeline flushes.We illustrate our scheme with Move Elimination (shortcircuiting moves) and an implementation of Speculative Memory Bypassing (short-circuiting store-load pairs) that makes use of a TAGE-like predictor to identify memory dependencies. We show that the whole potential of these two mechanisms can be achieved with a small register tracking structure.

Register sharing for equality prediction

“…Physical register sharing is a powerful technique that enables move elimination [26], SMB [11], register integration [27] as well as other various rename-based optimizations [28], [29]. Nonetheless, sharing physical registers between instructions is not trivial because ownership of a register can change during execution as a result of a branch (or other) misprediction.…”

“…Many previous works assume the presence of per-register reference counters [26], [27], [28], [29], but those are problematic in the presence of checkpointing as reference counters do not straightforwardly lend themselves to checkpointing [11], [12], [13].…”

“…Perais and Seznec [11] proposed a dual-counter scheme. The first counter tracks the number of references to a physical register (speculative), while the second counter tracks the number of committed references (architectural).…”

“…Recently, [11] applied the same scheme but considered bypassing from both stores and loads using the IDist. They also considered a TAGE-like IDist predictor, which outperformed the gshare-like predictor of Sha et al [10].…”

“…As a result, we propose Register Sharing for Equality Prediction (RSEP). RSEP leverages recent propositions regarding physical registersharing schemes [11], [12], [13] to actually share the physical register between the predicted instruction and the older instruction.…”