40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology

Galal, Shereen M.; Razavi, Behzad

doi:10.1109/jssc.2004.835639

Cited by 143 publications

(61 citation statements)

References 7 publications

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“…15. The amplifier has a measured gain of 7 dB at 130 GHz and 6.1 dB at 135 GHz with a 3-dB bandwidth over 30 GHz from 117 to 148 GHz which can be used for 40 Gb/s transmission system [5]. The circuit draws 53 mA current from a supply of 1.5 V. When the supply voltage is set to 2.5 V, the gain of 6.5 dB can be achieved at 135 GHz, but the efficiency will be degraded.…”

Section: Resultsmentioning

confidence: 99%

A D-Band Power Amplifier With 30-GHZ Bandwidth and 4.5-DBM Psat for High-Speed Communication System

Zhang¹,

Xiong²,

Wang³

et al. 2010

PIER

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Abstract-This paper presents a D-band power amplifier for highspeed communication system. The capacitive effect of interconnection via on transistor performance at high frequency is analyzed and a new via structure is employed to reduce the capacitive effect. The on-chip matching technique for high frequency amplifier is analyzed and the thin-film microstrip line matching network is used, which is combined with biasing network to reduce RF signal loss and silicon cost. The amplifier is fabricated in 0.13-µm SiGe BiCMOS process. The experimental results show a 7 dB gain at 130 GHz with 3-dB bandwidth of 30-GHz. The input return loss is better than 10 dB over 23 GHz. In addition, this amplifier achieves saturated output power (P sat ) of 4.5 dBm and input 1-dB gain compression point (P 1 dB ) of −4.5 dBm. The chip size of implemented power amplifier is only 0.22 mm 2 .

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Section: Resultsmentioning

confidence: 99%

A D-Band Power Amplifier With 30-GHZ Bandwidth and 4.5-DBM Psat for High-Speed Communication System

Zhang¹,

Xiong²,

Wang³

et al. 2010

PIER

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“…Different approaches were proposed for bandwidth extension such as f T doubler , negative impedance converter , negative Miller capacitance Mataya et al, 1968), distributed amplifier (DA) (Arbabian & Niknejad, 2008;Chien & Lu, 2007), and inductive peaking technique (Mohan et al, 2000;Galal & Razavi, 2004), as shown in Fig. 7.…”

Section: Design Techniques For Broadband Amplifiersmentioning

confidence: 99%

“…The circuit analysis presented in the original publication (Galal & Razavi, 2004) shows a BWER up to 3.46 with a gain peaking of 1.8 dB based on the assumption that C g /C d is one. However, the BWER reduces to 1.83 when C g /C d of 3 is used, as shown in Fig.…”

Section: Shunt-series Peakingmentioning

confidence: 99%

Design Techniques for Microwave and Millimeter Wave CMOS Broadband Amplifiers

Hsu¹,

Jin²

2010

Microwave and Millimeter Wave Technologies Modern UWB Antennas and Equipment

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“…Signal degradation is a key issue with high speed communication circuits. With this issue, peaking techniques are used in a high-speed communication circuit for compensation [6][7][8][9][10]. The peaking circuit realizes compensation characteristics by emphasizing the highfrequency component.…”

Section: Introductionmentioning

confidence: 99%

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

Tanaka¹,

Kishine²,

Tsuchiya³

et al. 2016

IEIE Transactions on Smart Processing and Computing

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Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

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40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology

Cited by 143 publications

References 7 publications

A D-Band Power Amplifier With 30-GHZ Bandwidth and 4.5-DBM Psat for High-Speed Communication System

A D-Band Power Amplifier With 30-GHZ Bandwidth and 4.5-DBM Psat for High-Speed Communication System

Design Techniques for Microwave and Millimeter Wave CMOS Broadband Amplifiers

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

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