40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate

Wang, Chua-Chin; Hou, Zong-You; Huang, Ssu-Wei

doi:10.1109/apccas.2018.8605678

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate

Cited by 5 publications

References 9 publications

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

2.5 GHz Data Rate 2 × VDD Digital Output Buffer Design Realized by 16-nm FinFET CMOS

Contact Info

Product

Resources

About