40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Chiu, Yi; Hu, Yu; Tu, Ming Hsien; Zhao, Jun; Chu, Yen-Ming; Jou, Shyh-Jye; Chuang, Ching Te

doi:10.1109/tcsi.2014.2332267

Cited by 114 publications

(71 citation statements)

References 21 publications

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“…22 Write static noise margin is determined from the write butterfly curve, which is the side length of the smallest square inscribed in write butterfly curve. It is 9×, 1.2×, 1.7×, and 1.94× higher when compared with the WSNM value of 6T, 12T J.Kim, 18 DAWA12T, 5 and PPN10T, 12 respectively, at 0.4-V V DD . It is 9×, 1.2×, 1.7×, and 1.94× higher when compared with the WSNM value of 6T, 12T J.Kim, 18 DAWA12T, 5 and PPN10T, 12 respectively, at 0.4-V V DD .…”

Section: Write Ability With Ddfcmentioning

confidence: 78%

“…Lower NMOSFETs (M1, M2) are controlled by the bit line and thus facilitates the data-dependent feedback cutting (DDFC). 5,12,18 Table 2 provides the structural comparison of different SRAM cells. The stacking effect, which is formed by the use of two series connected NMOS devices in write access path and also in the inverter pair, increases the equivalent resistance of the paths and therefore helps to control the overall leakage power of the proposed cell.…”

Section: Robust Low-power Half-select Free 12t Srammentioning

confidence: 99%

“…7 To address these issues, various bit cells have been proposed. 5 In addition, these implementations also demand for additional circuitry to generate the data-dependent control signals. However, any effective strategy to improve the write ability was absent in this solution.…”

Section: Introductionmentioning

confidence: 99%

“…4 However, designing a resilient SRAM operating in near-threshold or subthreshold region is extremely challenging due to the increased effect of process, voltage, and temperature (PVT) variations. 5 Therefore, the use of conventional 6T SRAM cell at a low-supply voltage (< 2V TH ) operation is not preferable due to the reduced noise margin, which leads towards a higher probability of the cell malfunctioning. 6 Read disturb, half-select destruction, and read-write conflict are other major issues of conventional 6T cell at low-supply voltage.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

Sharma

Vishvakarma

Chouhan

et al. 2018

Circuit Theory & Apps

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In this work, a data-dependent feedback-cutting-based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state-of-the-art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results.Finally, a small SRAM macro along with its independent memory controller has been designed. KEYWORDS circuit design, low-power, SRAM, stability, write ability 2314

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Section: Write Ability With Ddfcmentioning

confidence: 78%

Section: Robust Low-power Half-select Free 12t Srammentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

Sharma

Vishvakarma

Chouhan

et al. 2018

Circuit Theory & Apps

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show abstract

“…reduction and widely adopted in practical applications [3]- [9]. However, lowering supply voltage can also lead to the reduction of nodal critical charge, which imposes serious soft error threats on the reliable operations of SRAMs [10].…”

mentioning

confidence: 99%

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Chen

et al. 2015

IEEE Trans. Nucl. Sci.

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Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally characterized to determine their appropriate applications in radiation environments. This characterization is especially important when low supply voltage is preferred. In this paper, we developed an SRAM test chip with four cell arrays including two types of unhardened cells (standard 6T and subthreshold 10T) and two types of hardened cells (Quatro and DICE). This test chip was fabricated in a 65 nm bulk technology and irradiated by heavy ions at different supply voltages. Experimental results show that the SERs of 6T and 10T cells present significant sensitivities to supply voltages when the particle linear energy transfers (LETs) are relatively low. For Quatro and DICE cells, one does not consistently show superior hardening performance over the other. It is also noted that Quatro cells show significant advantage in single event resilience over 10T cells although they consume similar areas. TCAD simulations were carried out to validate the experimental data. In addition, the error amount distributions follow a Poisson distribution very well for each type of cell array.

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Cited by 114 publications

References 21 publications

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

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