A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

SummaryOver the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm2 physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.

Section: Introductionmentioning

confidence: 99%

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Jooq

Bozorgmehr

Mirzakuchaki

2020

“…Different techniques have been executed for limiting the power utilization in which the voltage scaling is one of the most favored options for both the switching and leakage power. However, designing SRAM at subthreshold region is very crucial because of the expanded impact of process, voltage, and temperature (PVT) variations . Presently, to support Moore's Law, it is important to search for alternate devices like fin‐shaped field effect transistors (FinFETs), tunneling field effect transistor (TFETs), and CNFET that have a considerable recognition in the last couple of years as a promising augmentation to CMOS technology .…”

Section: Introductionmentioning

confidence: 99%

“…However, designing SRAM at subthreshold region is very crucial because of the expanded impact of process, voltage, and temperature (PVT) variations. 4 Presently, to support Moore's Law, it is important to search for alternate devices like fin-shaped field effect transistors (FinFETs), tunneling field effect transistor (TFETs), and CNFET that have a considerable recognition in the last couple of years as a promising augmentation to CMOS technology. 5 The carbon nanotube offers audacious channel scaling because of its ultraminiature size of the body, whereas the ON current is very high due to built-in/inherent transfer characteristics.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Kumar

Ubhi

2019

Summary The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.

“…Such cameras are further used in mobile vehicle license plate detection services and are analyzed in terms of energy‐delay product etc. Bit interleaved SRAM is proposed in Sharma et al with static noise margin, read stability, and reduced standby power. Analytical model for write margin is simulated using Monte Carlo simulation to prove the better performance of SRAM.…”

Section: Introductionmentioning

confidence: 99%

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha

Shylu

Nagabushanam

2019

Summary Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.