Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Memory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low-power, high-performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT-MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT-MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT-MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT-MRAM cells, this article presented an optimum STT-MRAM cell design based on PMA-MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT-MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.IP (in-plane), MTJ (magnetic tunnel junction), PMA (perpendicular magnetic anisotropy), STT-MRAM, write margin, write power | INTRODUCTIONSemiconductor memory devices and technologies, such as memory storage, are critical for data storage in electronics. Memory currently occupies more than 80% of the die area. This percentage is constantly increasing due to the continued reduction of the CMOS technology node below the 90-nm domain. Memory performance rises in terms of size and speed owing to technological scaling, while the static power consumption of CMOS-based memories increases due to an exponential growth in standby current. 1 Memory reliability is also impacted. The length of global interconnects

“…This is often specified as the tunneling magneto resistance (TMR) ratio, and this impact is defined as the TMR effect. The TMR ratio is given by Equation (1).…”

Section: Magnetic Tunnel Junctionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

Prasad¹,

Sahu²,

Mandi³

et al. 2021

“…In recent years, circuit designers have been working on scaling down the transistors. Therefore, various researches have been done to achieve an alternative for conventional metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) 2 . The carbon nanotube field‐effect transistor (CNTFET) technology with the potency of dimension reduction is a suitable choice for IC fabrication 3 .…”

Section: Introductionmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

“…The static power consumption constitutes the major component of total power consumption for an SRAM bit cell as the bit cell operates mostly in hold mode. There is a limitation in reducing the V DD as it slows down the memory operation that too with a significant increase in the bit error rate (BER) 6 . Thus, designing high‐performance digital circuits with V DD in the range of saturation voltage of a metal–oxide– semiconductor (MOS) transistor ( VDS sat ) is a real challenge for designers 7,8 …”

Section: Introductionmentioning

confidence: 99%

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Rawat

Mittal

2021

Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.