This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor. The design is implemented in 40-nm bulk CMOS, and it was integrated in silicon as part of a complete super-heterodyne receiver. In the proposed topology, cross-connected transconductors are used to boost the quality factor. The resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden. The passive filter is fully programmable, which allows for an intermediate frequency selection in the range of 20 MHz to 100 MHz. The consequent variable bandwidth enables its use for either narrowband or wideband applications. The passive filter, with transconductance amplification and clock generation, occupies an area of 0.24 x 0.28 mm 2 with a power consumption of 8 mW when operating with a 500 MHz sampling frequency.Index Terms-charge-sharing bandpass filter, discrete-time, noise, switched-capacitor.