40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data

Kimura, Takashi; Ito, Takashi; Tsuruda, Tamaki; Nishiyama, Tomohiro; Nagasawa, Tsutomu; Ogawa, Takahisa; Kawashima, Yasunaru; Hidaka, Hideto; Yamauchi, Takayoshi

doi:10.1109/isscc.2013.6487704

Cited by 26 publications

(10 citation statements)

References 3 publications

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“…DESIGN AND EVALUATION OF TEST CHIP Fig. 10 is a die photograph of the test chip using 40 nm embedded flash CMOS technology [10]. Table 2 presents a summary of the test chip features.…”

Section: Write and Read Disturb Issuesmentioning

confidence: 99%

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues

Yokoyama

Ishii

Tanaka

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation at temperatures of -40 to 170°C are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and to ensure the read/write operating margin at over 125°C, a new 8T SRAM bitcell with the optimized process and sizing is proposed. A test circuit for screening disturb failures for dual-port and two-port SRAMs is also proposed. Designed and fabricated test chips showed that measured V min is achieved under 0.7 V with good distribution. Results show that the proposed test circuits can screen the disturb failures effectively.

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“…DESIGN AND EVALUATION OF TEST CHIP Fig. 10 is a die photograph of the test chip using 40 nm embedded flash CMOS technology [10]. Table 2 presents a summary of the test chip features.…”

Section: Write and Read Disturb Issuesmentioning

confidence: 99%

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues

Yokoyama

Ishii

Tanaka

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…3) read disturb in unselected cells is negligible as the voltage between MG and WELL, which is the dominant stressor in this case, is 0V. As a result, the proposed array architecture realizes a readdisturb-free operation and ensures automotive-grade reliability with high reliability via charge-trapping storage [1].…”

mentioning

confidence: 92%

“…A high-end engine-control unit (ECU) requires high-performance Flash MCUs, which integrate high-speed CMOS logic and large high-performance embedded Flash memories (eFlash) [1,2]. There are also broad markets for motor control MCUs: used to control actuators in parts such as seats, windows, and mirrors.…”

mentioning

confidence: 99%

7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C

Mitani

Matsubara

Yoshida

et al. 2016

2016 IEEE International Solid-State Circuits Conference (ISSCC)

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The computerization of automotive control has expanded the application range of micro controller units (MCUs). A high-end engine-control unit (ECU) requires high-performance Flash MCUs, which integrate high-speed CMOS logic and large high-performance embedded Flash memories (eFlash) [1,2]. There are also broad markets for motor control MCUs: used to control actuators in parts such as seats, windows, and mirrors. In order to integrate analog circuits to control the high voltage (HV) drivers in these parts, those MCUs have been manufactured in Flashless process, and external EEPROM chips are being used. EEPROM chips work as "learning memories" which store the calibration data to optimize analog circuit performance in the field. Replacement of external EEPROM chips by eFlash, resulting in less additional process cost and higher rewrite endurance, is a requirement for more elaborate learning at a higher data sampling rate. In addition to automotive grade reliability under extremely harsh temperature conditions, low power consumption is also a strong requirement as the number of MCUs used in motor control systems is increasing.This paper presents a one-transistor MONOS (1T-MONOS) eFlash macro for automotive applications, with four key features: 1) A 1T-MONOS cell with a low implementation cost, high reliability, and low power consumption thanks to FN tunneling program and erase (P/E) operations; 2) Read-disturb-free array architecture to ensure automotive grade reliability; 3) Adaptable slope pulse control (ASPC) technique that can achieve over 100M cycles of rewrite endurance at a 175°C junction temperature (Tj), and that can reduce total power consumption down to 0.07mJ/8kB using a 98μA P/E current; 4) 1T-MONOS-based low-power system-control scheme suitable for green car applications with a 99% power reduction.Figure 7.6.1 shows the 1T-MONOS cell, it is a simple 1T cell with charge-trapping ONO film and inherits cost merits typical for this type of a cell: less additional mask layers and process steps are needed to integrate memory cell formation modules into baseline process. Compared to a 2-transistor (2T) MONOS cell [3] with the same cell size, the 1T-MONOS cell stores more charges thanks to its wider ONO film area. Figure 7.6.1 also summarizes the voltage conditions required for each operation. P/E operations are based on FN tunneling, resulting in lowpower consumption. To adopt FN tunneling for P/E operations the ONO film thickness should be thinner, which is critical for read disturb. A 2T-MONOS cell is free from read disturb because the select transistor (SG) suppresses channel leakage even with a depleted erase cell. In contrast, the Vth of a conventional 1T-MONOS cell is set higher than 0V to suppress channel leakage of unselected cells in read operation. This is why conventional 1T-MONOS cell needs positive MG voltage in read operation and the selected one suffers from read disturb. Even worse, a 1T-MONOS cell with thinner ONO film becomes more vulnerable to read disturbs, that can be fatal in automotive u...

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“…Traditional dual-poly [2] and split-gate [3], [4] eFlash technologies are optimized for high-density nonvolatile code and data storage applications. The former employs a floating gate (FG) device while the latter utilizes charge trap material for achieving nonvolatile storage.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

Song

Kim

2014

IEEE Trans. Electron Devices

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Single-poly embedded flash (eFlash) memory is a unique category of embedded nonvolatile memory (eNVM) that can be built in a generic logic technology. Several single-poly eFlash cells have been proposed for cost-effective moderate density eNVM applications. However, the optimal cell configuration of single-poly eFlash is still under debate. In this paper, we compared various single-poly eFlash memory structures in terms of disturbance, program/erase speed, endurance, and retention characteristic based on simulated and experimental data from two eFlash test chips fabricated in a generic 65-nm logic process using standard 2.5 V I/O transistors with 5-nm tunnel oxide. We conclude that a 5T eFlash cell structure combining a pMOS coupling device, an NCAP tunneling device, and an nMOS read/program device with two additional pass transistors to support self-boosting is the most attractive option for logic-compatible eNVMs.Index Terms-Embedded flash (eFlash) memory, embedded nonvolatile memory (eNVM), single-poly eFlash.

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40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data

Cited by 26 publications

References 3 publications

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues

7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

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40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data

Cited by 26 publications

References 3 publications

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of &#x2212;40 to 170&#x00B0;C with test screening against write disturb issues

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of &#x2212;40 to 170&#x00B0;C with test screening against write disturb issues

7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C

A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic

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40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues