IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
DOI: 10.1109/iedm.2005.1609312
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45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process

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Cited by 5 publications
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“…In the conventional P incorporation process, P ions are implanted into a poly-Si gate before Ni silicide gate formation and introduced to the Ni silicide/SiO 2 interface with the ''snow-plow effect'' during silicidation (pre-doping process). [1][2][3][4][5][6][7]12) However, not only P segregation but also changes in crystallinity and Ni-Si ratio of the silicide layer occur in the pre-doping process. 6,8) These changes of the film structure make it difficult to evaluate the unadulterated effect of P segregation, since they are also possible causes of È eff modulation.…”
Section: Methodsmentioning
confidence: 99%
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“…In the conventional P incorporation process, P ions are implanted into a poly-Si gate before Ni silicide gate formation and introduced to the Ni silicide/SiO 2 interface with the ''snow-plow effect'' during silicidation (pre-doping process). [1][2][3][4][5][6][7]12) However, not only P segregation but also changes in crystallinity and Ni-Si ratio of the silicide layer occur in the pre-doping process. 6,8) These changes of the film structure make it difficult to evaluate the unadulterated effect of P segregation, since they are also possible causes of È eff modulation.…”
Section: Methodsmentioning
confidence: 99%
“…A nickel fully silicided (Ni-FUSI) gate is a good candidate for the metal gate electrode because of its process compatibility with the present large-scale integration fabrication and superior device performance. [1][2][3][4] The difficulty of effective work function (È eff ) control at the Ni-FUSI/gate dielectric interface is one of the major impediments to the application of a Ni-FUSI gate for future CMOS devices. È eff s corresponding to the Si conduction band edge (Si-E c $ 4:1 eV) and Si valence band edge (Si-E v $ 5:2 eV) are required for n-and p-type transistors to realize low threshold-voltage (V th ) operation in bulk CMOS devices, whereas the È eff of NiSi is about 4.6 eV, which corresponds to Si midgap level.…”
Section: Introductionmentioning
confidence: 99%
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“…Uma vantagem desta abordagem é que a função trabalho da porta pode ser ajustada por implantação de dopantes. O NiSi tem demonstrado ser muito bom candidato graças a seu comportamento como mid-gap e sua facilidade de integração pois a silicetação se faz em baixa temperatura 31 .…”
Section: Materiais De Porta Alternativosunclassified