45nm LSTP FET with FUSI Gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

Mitsuhashi, R.; Yamamoto, Kazuhiko; Hayashi, Shigenori; Rothschild, A.; Kubicek, Stefan; Veloso, A.; Elshocht, Sven Van; Jurczak, M.; Gendt, Stefan De; Biesemans, S.; Niwa, Miki

doi:10.1016/j.mee.2005.04.036

Cited by 6 publications

(3 citation statements)

References 4 publications

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“…Effect of the thin SiN capping on top of the high-k dielectric is investigated (14) . The EOT calculated from the CV curve of Ni-FUSI/HfO 2 without SiN cap is 1.0nm.…”

Section: Effect Of Sin Cappingmentioning

confidence: 99%

“…The above result implies that SiN cap can increase the transistor yield but it can not always provide better electrical properties. (a) Effect of PDA treatment -improvement of High-k film quality (14) PDA treatment strongly influence on the WF by modulating the oxygen vacancy (15). Comparison of I on -I off with respect to poly Si and Ni-FUSI/SiN/HfO 2 under PDA at 700C is shown in Fig.…”

Section: Effect Of Sin Cappingmentioning

confidence: 99%

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Prospect of Hf-Based Gate Dielectric by PVD with FUSI Gate for LSTP Application

Niwa¹,

Mitsuhashi

Hayashi

et al. 2006

ECS Trans.

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Study of Hf based high-k gate stack, HfO2 and its silicate, prepared by PVD-high k dielectric and Ni-Fully Silicide(FUSI) gate focusing on interfacial reaction between high-k and Ni- FUSI electrode is overviewed. Effects of SiN capping between Ni-FUSI gate and high-k dielectric and post deposition anneal (PDA) to suppress the reaction during FUSI process were investigated. The SiN cap could increase transistor yield and PDA could suppress instability of the drive current due to defects/roughness caused by interfacial reaction during NiSi formation. It is noteworthy that not only elimination of poly- depletion but also EOT reduction was observed by replacing the poly Si with the Ni-FUSI, which was remarkable for Ni- FUSI/SiON than HfO2 case. Hereof, by optimizing the PDA condition with SiN cap, decent electrical characteristics were obtained, Ion(n/p) > 600/200 uA/um at Ioff = 20 pA/um at Vdd = 1.1V. This drivability meets low stand-by power specification of the MOSFET for 45nm node.

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“…Effect of the thin SiN capping on top of the high-k dielectric is investigated (14) . The EOT calculated from the CV curve of Ni-FUSI/HfO 2 without SiN cap is 1.0nm.…”

Section: Effect Of Sin Cappingmentioning

confidence: 99%

Section: Effect Of Sin Cappingmentioning

confidence: 99%

Prospect of Hf-Based Gate Dielectric by PVD with FUSI Gate for LSTP Application

Niwa¹,

Mitsuhashi

Hayashi

et al. 2006

ECS Trans.

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“…HfO 2 is considered as a leading candidate for high-κ dielectric devices because of its high dielectric constant and good thermal stability in comparision to other oxide materials. The HfO 2 dielectric with κ 20 has been successfully applied to 45-nm silicon MOSFET devices [4,5]. However, the deposition of pure HfO 2 directly on In 0.53 Ga 0.47 As leads to a poor interface with considerably high density of interface traps (D it ) in the order of 10 13 cm −2 eV −1 closed to the In 0.53 Ga 0.47 As midgap [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

INVESTIGATION OF CHARGE TRAPS AT Al-DOPED HfO2/(100)InGaAs INTERFACE BY USING CAPACITANCE AND CONDUCTANCE METHODS

Hoang¹

2018

JST

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In this study, capacitance and conductance methods were used to investigate the charge traps at a HfO2/(100)InGaAs interface with an atomic layer deposition HfO2 layer doped with Al2O3 by co-deposition technique. The effect of Al doping on the quality of the HfO2/In0.53Ga0.47As interface will be evaluated. The density of interface traps (Dit) near In0.53Ga0.47As midgap is close to 2×1012 cm−2eV−1. Based on comparison to the HfO2/In0.53Ga0.47As interface without Al2O3 interfacial passivation where the value Dit∼1013 cm−2eV−1 is encountered near the midgap, we can conclude that the presence of Al2O3 passivation noticeably improves the interface quality.

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