48 V input rad-hard DCDC converters for HEP experiments: development and results

Antoszczuk, Pablo; Michelis, S.; Ripamonti, Giacomo; Saggini, S.; Iob, Federico

doi:10.1088/1748-0221/17/01/c01068

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…The output Q end of DFF2 is connected to the D end of DFF3, and the D input end of the DFF1, 2, 4, and 5 triggers is attached to Vdd. The output Q-terminals of DFF4 and 5 triggers in the figure are up and down, respectively [3]. The result of the up-down signal and the output Q of the DFF3 trigger is then delayed through a NAND gate and a buffer, serving as the reset signal for D4 and D5 triggers, with a delay of about 400 ps.…”

Section: Pfd Circuit Design and Simulation Analysismentioning

confidence: 99%

Design of A 12-phase Clock Generator Based on DLL

Zhang,

Wang,

Huang

2024

J. Phys.: Conf. Ser.

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This article proposes a 12-phase clock generator for DC-DC power supply chips, which can be used for external clock synchronization of DC-DC and serves as the foundation for multiple parallel connections of DC-DC. This article is based on the NTC 0.35 um BCD process and verified through simulation by using Cadence software. In typical environments of 3.3 V and 27°, the clock input range is 832 K-49.6 MHz, the time to reach stability is less than 5 us, the clock jitter is less than 1%, the duty cycle error is less than 3.5%, and the phase error generated is less than 1%.

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Section: Pfd Circuit Design and Simulation Analysismentioning

confidence: 99%

Design of A 12-phase Clock Generator Based on DLL

Zhang,

Wang,

Huang

2024

J. Phys.: Conf. Ser.

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Optimized rad-hard DC/DC converters for HEP applications

van der Blij,

Koseoglou,

Bantemits

et al. 2024

J. Inst.

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The development of 48 V compatible DC/DC converters that are tolerant to high magnetic fields and radiation helps to reduce the cost and weight of the cabling, power supplies and cooling of High Energy Physics (HEP) experiments. In this paper, a new, optimized and compact bPOL48V module is presented aimed at 48 V to 5–12 V power conversion. This new module, which is available for purchase and as a reference design, reduces the size by 93% compared to previous designs while exhibiting similar efficiency. Furthermore, a framework for optimizing and comparing converter topologies is also introduced, which identifies the 3-level buck topology as a promising topology for future research and development. Moreover, experimental validation of different optimized converters is also provided. The experimental results show that the 3-level buck topology is promising for 48 V to 5 V conversion stages, and that the Berkeley buck topology is promising for the development of 48 V to 1 V conversion stages.

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