480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition

Abstract

Abstract-A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (109 multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256×512 array of 3-T chargeconserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated on a face detection task.Index Terms-Adiabatic low-power techniques, resonant clock supply, computational memory, pattern recognition.

Low‐power adiabatic 9T static random access memory

“…As the use of static random access memory (SRAM) L2 caches in current consumer processors tends to substantially increase chip size, reducing the power consumption of SRAM remains a critical area of research. Since logics [1–14] and memories [15–21] employing the adiabatic principle can lower the limit on energy consumption in static complementary metal‐oxide semiconductors (CMOSs) devices, such structures show great potential for use in low‐power very large‐scale integration (VLSI) design. Adiabatic memories can be categorised into a number of types: static [15, 19, 20], latch [16, 17] and dynamic [18].…”

A Digital-Pixel-Sensor-Based Global Feature Extraction Processor for Real-Time Object Recognition

“…[1][2][3][4][5] Because these algorithms are computationally expensive, to achieve real time performances in object recognition tasks, very large scale integration (VLSI) chips such as digital signal processors (DSPs), field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) were developed to accelerate the computation. [6][7][8][9][10][11] In ref. 6, a highly parallel DSP architecture that can process many complex functions such as 5 Â 5 spatial filtering was designed for real-time image recognition.…”

“…In ref. 11, a resonant adiabatic mixed-signal ASIC was designed and a real-time template-based face detection function was realized as one application of this work. Therefore, with the power of such programmable VLSI chips, the processing speed of existing recognition algorithms can be clearly enhanced.…”

A new high speed, low power adder; using hybrid analog-digital circuits

“…However, recently, designers used both concepts of analog and digital circuit design to achieve hybrid processors with positive properties of both analog and digital circuits [9][10][11][12][13]. In this paper also we've used hybrid analog-digital circuits to make and adder with better properties (i.e.…”