4H–SiC Lateral Double RESURF MOSFETs With Low on Resistance

Noborio, Masato; Suda, Jun; Kimoto, Tsunenobu

doi:10.1109/ted.2007.894249

Cited by 45 publications

(36 citation statements)

References 26 publications

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“…And the trade-off between the breakdown voltage (BV) and the current capability for the LDMOS is always a hot topic in the research area of power devices [1,2,3]. The buried-pwell under the n-drift region is a frequentlyused method in bulk silicon process to reduce surface field (RESURF) and achieve the trade-off between BV and current capability.…”

Section: Introductionmentioning

confidence: 99%

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Zhang

Liu

Sun

et al. 2014

IEICE Electron. Express

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A novel lateral double diffused MOSFET (LDMOS) structure with partial buried-oxide layer under the n-drift region, which is suitable for the bulk silicon epitaxial process, is proposed. The introduction of the buried-oxide layer produces an inversion layer at buried-oxide/p-sub interface and achieves better reduced surface field (RESURF) effect comparing with the conventional device with buried-pwell. Moreover, the buried-oxide can prevent the impurity diffusion and improve the doping concentration of the ndrift region. As a result, the proposed structure improves the breakdown voltage about 12% and increases the current capability over 30% at the same time.

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Section: Introductionmentioning

confidence: 99%

A lateral DMOS with partial buried-oxide layer to achieve better RESURF effect

Zhang

Liu

Sun

et al. 2014

IEICE Electron. Express

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“…High-voltage lateral double-implanted MOSFETs implemented on high-purity semi-insulating 4H-SiC substrates with gate field plates 1. Introduction 4H-SiC lateral MOSFETs have attractive attention as a key component for high-voltage power IC applications owing to their wide bandgap properties providing high critical E-field and low on-resistance.…”

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confidence: 99%

“…Introduction 4H-SiC lateral MOSFETs have attractive attention as a key component for high-voltage power IC applications owing to their wide bandgap properties providing high critical E-field and low on-resistance. [1][2][3] Recently, they have also been applied to harsh-environment systems such as high-temperature and radiation-exposure conditions in power plants and aerospace. 3,4) 4H-SiC lateral MOSFETs are typically fabricated on a low-doped epitaxial layer on conducting substrates with off-orientation to simplify the formation of n-or p-well region.…”

mentioning

confidence: 99%

“…3,4) 4H-SiC lateral MOSFETs are typically fabricated on a low-doped epitaxial layer on conducting substrates with off-orientation to simplify the formation of n-or p-well region. [1][2][3][4] In the case of epitaxially grown substrates, offorientation is employed to prevent the poly-type inclusion phenomenon during epitaxial growth for the low-doped layer. 5,6) However, the off-orientation of 4H-SiC causes serious surface scattering for electrons at the interface between 4H-SiC and the gate insulator in the lateral MOSFETs.…”

mentioning

confidence: 99%

“…For the SiC lateral MOSFETs on a low-doped epitaxial layer, a reduced surface field (RESURF) structure has been reported. 1,19) For the design of RESURF, the opposite polarity of a RESURF region against the epitaxial layer while considering the background doping concentration should be incorporated. In the case of semiinsulating substrates, RESURF structures may not be suitable owing to the extremely low background carrier concentration.…”

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confidence: 99%

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High-voltage lateral double-implanted MOSFETs implemented on high-purity semi-insulating 4H-SiC substrates with gate field plates

Seok

Kim

Moon

et al. 2018

Jpn. J. Appl. Phys.

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Lateral double-implanted MOSFETs (LDIMOSFETs) fabricated on on-axis high-purity semi-insulating (HPSI) 4H-SiC substrates with gate field plates have been demonstrated for the enhancement of reverse blocking capability. The effects of gate field plate on LDIMOSFET were analyzed by simulation and experimental methods. The electric field concentration at the gate edge was successfully suppressed by a gate field plate. A high breakdown voltage of 934 V and a figure of merit of 14.6 MW/cm 2 were achieved at L FP of 2 µm and L drift of 15 µm, while those of the conventional device without a gate field plate were 744 V and 13.3 MW/cm 2 , respectively. Also, the fabricated device shows stable blocking characteristics at a high temperature of 250 °C. The drain leakage was increased by only 22% at 250 °C compared with that at room temperature.

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